High-performance global routing with fast overflow reduction

Chen, Guihai; Hsü,; Chang, Yao-Wen

doi:10.1109/aspdac.2009.4796543

Cited by 48 publications

(32 citation statements)

References 14 publications

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“…Here, Mi denotes the i th metal layer. CATALYST differs from the traditional layer assignment step in global routing [3]- [8], which assigns the wires to different layers as a last step to complete the routing of a net. In contrast, CATALYST generates layer directive constraints for timing-critical nets, and these directives are propagated throughout the physical synthesis flow.…”

Section: A Layer Directives and Notationsmentioning

confidence: 99%

“…Most of the previous related works are from the global and detailed routing literature, but do not address the problem of early planning for layer assignment. Conventional routers perform layer assignment purely for routing congestion minimization and many works focus on how to perform layer assignment with via minimization [3]- [8]. In these works, the timing benefit of thick layers is not leveraged at all.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

CATALYST: Planning Layer Directives for Effective Design Closure

Wei

Sze

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion-and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm. I. INTRODUCTIONPhysical synthesis is a critical component of modern design methodologies, enabling timing closure at the physical design stage. Technology scaling brings new challenges and opportunities to physical synthesis. Wire resistance per unit length increases quadratically with technology scaling and results in significant increases in wire delay. However, recent work [1], [2] shows that the availability of thicker wires in higher metal layers could potentially relieve this problem. At 65 nm technology, there are four 1× layers, three 2× layers and two 4× layers (Fig. 3). On a 2× layer, the single-width wires are 2× thicker and 2× wider than those on 1× layer, and therefore the per-unit wire resistance is reduced by roughly 4× (the per-unit capacitance is roughly similar across all layers, which is ensured by design rules including wire spacing and process specifications such as inter-layer dielectric thickness), greatly compensating for technology scaling effects. On the 2× [4×] layer, signals can roughly go 1.7× [2.5×] faster, with 2× [4.4×] reduction in buffer resources. Therefore, the difference in wire delays in different layers provides another dimension to timing optimization, beyond gate/wire sizing and buffering. Assigning timingcritical nets to thick layers can reduce area/power and improve timing closure by reducing delays and the buffer count. As illustrated in Fig. 1, the slack for a two-pin net A on a 4× layers is improved from -10 ps to 10 ps as compared to the corresponding route on the 1× layer, and the number of buffers is reduced from 7 to 1. Moreover, by using thick layers wisely, it could be shown that a 31% reduction on buffer area averaged over several industrial circuits can be achieved (Sec. VI-B). On the other hand, there are limited resources on thicker layers, and if too many nets are assigned to thicker layers, the design may not be routable or have large post-routing timing degradation.

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Section: A Layer Directives and Notationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CATALYST: Planning Layer Directives for Effective Design Closure

Wei

Sze

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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“…Probabilistic methods are highly inaccurate and fail to capture the behavior of global routing, especially in modern designs with numerous IP blockages and a large number of metal layers with varying width and spacing. Lately, the third method has become more attractive and mainstream due to the advent of fast, high-quality global routers [Xu et al 2009;Chang et al 2008;Cho et al 2007;Chen et al 2009;Wu et al 2010]. Although global-routing-based congestion analysis provides a happy medium between probabilistic analysis and detailed routing, it suffers from two key drawbacks.…”

Section: Introductionmentioning

confidence: 99%

Techniques for scalable and effective routability evaluation

Wei

Sze

Viswanathan³

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast design closure can only be achieved by accurately evaluating whether a design is routable or not early in the design cycle. Lately, it has become common to use a "light mode" version of a global router to quickly evaluate the routability of a given placement. This approach suffers from three weaknesses: (i) it does not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing, (ii) the congestion maps obtained by it tend to have isolated hot spots surrounded by noncongested spots, called "noisy hot spots", which further affects the accuracy in routability evaluation, (iii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer; moreover, they may often fail to predict the routability accurately. This paper presents solutions to these issues. First, we propose three approaches to model local routing resources. Second, we propose a smoothing technique to reduce the number of noisy hot spots and obtain a more accurate routability evaluation result. Finally, we develop a new metric which represents congestion maps with higher fidelity. We apply the proposed techniques to several industrial circuits and demonstrate that one can better predict and evaluate design routability, and congestion mitigation tools can perform much better to improve the design routability.

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“…Specifically, among the two categories of concurrent and sequential procedures, the latter became very popular recently to handle large-sized problem instances [8], [31], [23], [22], [26], [9]. However, an inherent downside of the sequential procedures is their high dependence on properties such as the ordering of the nets or the definition of empirical cost functions.…”

Section: Introductionmentioning

confidence: 99%

GRIP: Global Routing via Integer Programming

Davoodi

Linderoth

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This work introduces GRIP, a global routing technique via integer programming. GRIP optimizes wirelength and via cost directly without going through a traditional layer assignment phase. Candidate routes spanning all the metal layers are generated using a linear programming pricing phase that formally accounts for the impact of existing candidate routes when generating new ones. To make an integer-programmingbased approach applicable for today's large-scale global routing instances, the original problem is decomposed into smaller subproblems corresponding to rectangular subregions on the chip together with their net assignments. Route fragments of nets that fall in adjacent subproblems are connected in a flexible manner. In case of overflow, GRIP applies a second-phase optimization that explicitly minimizes overflow. By using integer programming in an effective manner, GRIP obtains high-quality solutions. Specifically, for the ISPD 2007 and 2008 benchmarks, GRIP obtains an average improvement in wirelength and via cost of 9.23% and 5.24%, respectively, when compared to the best result in the open literature.

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High-performance global routing with fast overflow reduction

Cited by 48 publications

References 14 publications

CATALYST: Planning Layer Directives for Effective Design Closure

CATALYST: Planning Layer Directives for Effective Design Closure

Techniques for scalable and effective routability evaluation

GRIP: Global Routing via Integer Programming

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