High-performance, hysteresis-free carbon nanotube field-effect transistors via directed assembly

Abstract

High-performance single-wall carbon nanotube field-effect transistors (SWNT-FETs) are fabricated using directed assembly and mass-produced carbon nanotubes (CNTs). These FETs exhibit operating characteristics comparable to state-of-the-art devices, and the process provides a route to large-scale functional CNT circuit assembly that circumvents problems inherent in processes relying on chemical vapor deposition (CVD). Furthermore, the integration of hydrophobic self-assembled monolayers (SAMs) in the device structure eliminates the primary source of gating hysteresis in SWNT-FETs, which leads to hysteresis-free FET operation while exposing unmodified nanotube surfaces to ambient air.Carbon nanotubes have remarkable physical and electrical properties that distinguish them as ideal components for nano-and molecular electronics 1 . Efforts devoted to incorporating them in device fabrication are probably best highlighted by progress in FETs 2-7 , which are fundamental to many nanotube-based applications from computing to sensing. So far, however, most high-performance 1 CNT-FETs have been fabricated using SWNTs grown on-substrate via CVD, while devices produced through 'directed assembly' and/or utilizing mass-produced have tried to keep pace. Nevertheless, CVD tends to produce large-diameter, small bandgap nanotubes, and the high-temperatures involved in the growth process often preclude integration with pre-existing circuit structures. For such reasons, high-performance FETs made by procedures more compatible with conventional semiconductor fabrication techniques are desirable and may represent a precursor to large-scale CNT circuit assembly for future industrial applications. Here, we demonstrate the directed-assembly 8,9 of SWNT-FETs using nanotubes grown by high-pressure decomposition of carbon monoxide (HiPCO), which produces large quantities of small-diameter, semiconducting SWNTs. These devices exhibit operating characteristics comparable with state-of-the-art FETs based on SWNTs from various sources, including CVD 10-12 .Notably, our devices can be operated free of gating hysteresis while exposing clean SWNT surfaces to ambient air. Previously, this hysteresis-free operation was possible only by encasing the FET in a polymer 13 , rendering it difficult for further circuit integration and inoperable for certain applications, such as sensing. Furthermore, since our method does not require any high-temperature processing steps, it is compatible with conventional semiconductor device fabrication processes.The SWNT-FETs are prepared by adapting a directed assembly technique 8 involving the controlled deposition of methyl-terminated (-CH 3 ) SAMs. These monolayers are placed either by microcontact printing or immersion to functionalize the metal electrodes and gate insulator, thereby creating a template for the subsequent placement and alignment of nanotubes. The schematic diagram depicting this procedure is shown in Figs. 1a-d. Five sets of source-drain electrodes each having a ~1-2 μm wide x 100 μm long gap ar...

Sorting Semiconducting Single-Walled Carbon Nanotubes and Using Them as Random Network of Field-Effect Transistors

“…7(a)]; these are attributed to the existence of impurities such as H 2 O, as reported by other researchers. 44,45 Our data con¯rm these results, and shows that the properties …”

Deposition and meniscus alignment of DNA–CNT on a substrate

“…Meniscus combing has also been used in layer-by-layer [13,14] assembly of carbon nanotubes and to shape nanotubes into ropes and rings [15]. One precise method of depositing carbon nanotubes is by patterning the surface with different monolayers to influence where the CNT deposits on the surface [16][17][18]. A similar method patterns a PDMS substrate, then transfer-prints CNTs from the substrate [19] onto a target surface.…”

Hysteresis reversion in graphene field-effect transistors

“…8 Hysteresis loop of the source-drain current ͑I sd ͒ in a cyclic sweep of gate voltage ͑V g ͒ has been observed in graphene, 9,10 graphene oxide, 11,12 and carbon nanotubes. [13][14][15][16] The hysteresis was usually ascribed to the environmental interactions from substrates and adsorbates. Several mechanisms, including charge trapping by water molecules bounded on SiO 2 substrate surface, charge trapping inside the insulating substrate, and dynamic screening of gate voltage have been proposed to explain the hysteresis.…”