High-performance IP routing table lookup using CPU caching

Chiueh, Tzi‐cker; Pradhan, Prashant

doi:10.1109/infcom.1999.752162

Cited by 90 publications

(34 citation statements)

References 13 publications

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“…Some of them compress the trie for decreasing the memory consumption and improving the speed [1][2], [19][20][21]. Since a binary trie needs lots of comparisons and memory accesses, many solutions use multibit trie concept to accelerate the lookup search [3][4][5][6][7][8][9][10][11][12][13]; however, using a multi-bit trie instead of binary trie normally increases the memory consumption. Some papers have proposed compression methods for solving this problem [8]- [13].Compression methods usually suffer from update overhead.…”

Section: E Related Workmentioning

confidence: 99%

Tree-Combined Trie: A Compressed Data Structure for Fast IP Address Lookup

Tahir¹,

Ahmed²

2015

ijacsa

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Abstract-For meeting the requirements of the high-speed Internet and satisfying the Internet users, building fast routers with high-speed IP address lookup engine is inevitable. Regarding the unpredictable variations occurred in the forwarding information during the time and space, the IP lookup algorithm should be able to customize itself with temporal and spatial conditions. This paper proposes a new dynamic data structure for fast IP address lookup. This novel data structure is a dynamic mixture of trees and tries which is called TreeCombined Trie or simply TC-Trie. Binary sorted trees are more advantageous than tries for representing a sparse population while multibit tries have better performance than trees when a population is dense. TC-trie combines advantages of binary sorted trees and multibit tries to achieve maximum compression of the forwarding information. Dynamic reconfiguration of TCtrie, made it capable of customizing itself along the time and scaling to support more prefixes or longer IPv6 prefixes. TC-trie provides a smooth transition from current large IPv4 databases to the large IPv6 databases of the future Internet.

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Section: E Related Workmentioning

confidence: 99%

Tree-Combined Trie: A Compressed Data Structure for Fast IP Address Lookup

Tahir¹,

Ahmed²

2015

ijacsa

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“…It has been demonstrated that a cache aware algorithm can speedup greatly an application that involves heavy data-retrieving [2,5]. In the following section, we provide a fast cache aware scheduling algorithm to accelerate the simulation of large scale communication networks.…”

Section: The Calendar Queue Schedulingmentioning

confidence: 99%

“…Both cache based method and cache aware method have been applied successfully in some heavy data-retrieving algorithms, including IP routing table lookup [5] and Radix tree implementation [2], where a huge amount of data are frequently accessed. This situation happens for a large scale DES as well, and CPU caching is benefit to speed up event scheduling.…”

Section: Introductionmentioning

confidence: 99%

The Speedup of Discrete Event Simulations by Utilizing CPU Caching

Wang¹,

Yang²

2012

Discrete Event Simulations - Development and Applications

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“…Chiueh et al [6] use a combined hardware/software approach to construct a cache for high performance IP routing in general-purpose CPU based routers. The destination host address is mapped to a virtual address space and used to lookup a destination route in the Host Address Cache (HAC).…”

Section: Locality and Caching In Network Processorsmentioning

confidence: 99%

Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors

Venkatesh

Calder

et al. 2005

High Performance Embedded Architectures and Compilers

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Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a traditional processor, and provide no additional throughput for a balanced network processor design. This is why most high end routers do not use caches for their data plane algorithms. In this paper we examine how to use a cache for a balanced high bandwidth network processor. We focus on using a cache not as a latency saving mechanism, but as an energy saving device. We propose using a Computation Reuse Cache that caches the answer to a query for dataplane algorithms, where the tags are the inputs to the query and the block the result of the query. This allows the data-plane algorithm to perform a complete query in one cache access if there is a hit. This creates slack by reducing the number of instructions executed. We then exploit this slack by fetch-gating the data-plane algorithm while matching the worst case throughput guarantees of the rest of the network processor. We evaluate the computation reuse cache for network data-plane algorithms IP-lookup, Packet Classification and NAT protocol.

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High-performance IP routing table lookup using CPU caching

Cited by 90 publications

References 13 publications

Tree-Combined Trie: A Compressed Data Structure for Fast IP Address Lookup

Tree-Combined Trie: A Compressed Data Structure for Fast IP Address Lookup

The Speedup of Discrete Event Simulations by Utilizing CPU Caching

Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors

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