High-Performance NB-LDPC Decoder With Reduction of Message Exchange

Lacruz, Jesus O.; García-Herrero, Francisco; Canet, M. J.; Valls, Javier

doi:10.1109/tvlsi.2015.2493041

Cited by 17 publications

(13 citation statements)

References 27 publications

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“…In order to compare our decoder with previous proposals implementing the same code, we synthesized the designs from [9][10][11][12] for the GF(64) code. We could not obtain post-layout results due to the high gate count of the designs.The results are summarized in Table V, where Table V, it can be seen that the highest reduction in the gate account is about 61% compared to the work from [9], and the lowest is 12% compared to the proposal from [11].…”

Section: A Decoder Implementation Results and Comparisonsmentioning

confidence: 99%

“…The information exchanged between processors is reduced from q × d c reliabilities to 4 × (q − 1) + d c messages without introducing any performance loss. A step further was taken in [12], where the mT-MM algorithm was proposed. This algorithm reduces the cardinality of the intrinsic information to only two elements, and the rest q − 2 values are approximated by a constant value.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Lacruz

García-Herrero

Canet

et al. 2016

IEEE Trans. VLSI Syst.

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Section: A Decoder Implementation Results and Comparisonsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Lacruz

García-Herrero

Canet

et al. 2016

IEEE Trans. VLSI Syst.

Self Cite

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“…In terms of gate count, despite he fact that [34] requires 21% less gates, our work achieves a throughput which is almost seven times higher due to the parallel processing used in the CN. Compared to the proposal from [56], our approach has similar throughput and outperforms it almost 6% in area, thanks to the reduction of complexity in the CN with the hardware structures presented in Section. 7.4.…”

Section: Decoder Implementation Results and Comparisonsmentioning

confidence: 91%

“…In order to compare our decoder with previous proposals implementing the same code, we synthesized the designs from [42,50,53,56] for the GF(64) code. We could not obtain post-layout results due to the high gate count of the designs.The results are summarized in Table 7.5, where we also show the implementation results of our decoder for L = 4 and L = 5.…”

Section: Decoder Implementation Results and Comparisonsmentioning

confidence: 99%

“…The information exchanged between processors is reduced from q × d c reliabilities to 4 × (q − 1) + d c messages without introducing any performance loss. A step further was taken in [56], where the mT-MM algorithm was proposed. This 121 algorithm reduces the cardinality of the intrinsic information to only two elements, and the rest q − 2 values are approximated by a constant value.…”

Section: Discussionmentioning

confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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Medical data transmission using the product of TLDPC and BCH error control coding systems with two interleavers

Kamalakannan¹,

Kalpana

2020

Int J Communication

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SummaryMedical data are very precious since it has the most sensitive data of patient which can save them. If it is handled wrongly or it is manipulated, then it could result in permanent problems or even it can result in fatal. So medical data widely used in a digital format with error detection and correction codes (EDC) in its transmission and storage process. EDC is a method of adding redundant bits to the static message bits to enhance the reliability of binary digital data broadcast while the medical data communication medium adds the errors in the course of transmission. In the proposed method, we use Bose–Chaudhuri–Hocquenghem codes (BCH) as an outline algorithm and trellis Low‐Density Parity Check code (TLDPC) as an inner algorithm along with two interleavers. Product of BCH code and TLDPC code with interleavers can control more errors as compared with its plain code and product of RS‐Hamming code. MATLAB used as a simulation tool. Plain BCH code is simulated first, and then plain LDPC code is simulated for the same information. Finally, the product of BCH and TLDPC with two interleavers is imposed on the same information. The result of our research work shows enhancement in bit error rate (BER) compared to other plain and product codes from 10−2 to 10−3. Also, frame error rate (FER) is improved in 0.5 scaling factors when compared with other trellis decoders. Hence, this proposed system can be utilized in an application where less error rate and high accuracy of information transmission between medical data processing systems are required.

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High-Performance NB-LDPC Decoder With Reduction of Message Exchange

Cited by 17 publications

References 27 publications

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

VLSI algorithms and architectures for non-binary-LDPC decoding

Medical data transmission using the product of TLDPC and BCH error control coding systems with two interleavers

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