High performance non-volatile memory with the control of charge trapping states in an amorphous InSnZnO active channel

Abstract

In this study, the influence of interface states between an indium tin zinc oxide (ITZO) active layer and a gate insulator on memory characteristics was examined as a function of annealing temperature. The annealing nonvolatile memory (NVM) devices have shown the best electrical characteristics such as high field effect mobility (27.22 cm 2 V −1 s −1 ), low threshold voltage (0.15 V), low subthreshold slope (0.17 V dec −1 ), and high on/off current ratio (7.57 × 10 7 ) in comparison with as-deposited devices. By annealing at 250 °C, the number of ITZO/insulator interface trap densities was reduced. The effect of the remaining trap states on the retention characteristic of memory devices is negligible. The performance of NVM devices using different annealing temperatures of ITZO and a multi-stack gate insulator SiO 2 /SiO x /SiO x N y with Si-rich SiO x for the charge storage layer was also reported. The 250 °C annealed ITZO-based NVM device showed a retention exceeding ∼94% of the threshold voltage shift after 10 4 s and greater than ∼90% after 10 years with a low operating voltage of +11 V at only 1 μs programming duration time. Therefore, the NVM devices, which were fabricated by the low ITZO/insulator interface trap densities, were highly suitable for potential application in memory systems.

Superior Atomic Layer Deposition Technology for Amorphous Oxide Semiconductor Thin-Film Transistor Memory Devices

“…5,6,31,34−39 Yi's group used an inductively coupled plasma chemical vapor deposited SiO x (Si-rich SiO x ) film as a charge storage layer for a-IGZO and amorphous InSnZnO (a-ITZO) TFT memories. 35,36 Although both of the memories show a high programming efficiency, it is demonstrated that they have a difficulty in electrical erasing. As an example, the a-ITZO TFT memory cannot show the shift of V th to the negative bias even with negative biasing from −10 to −30 V for 1 ms. 36 This is because the SiO x charge storage layer contains a number of traps including shallow and deep traps.…”

“…35,36 Although both of the memories show a high programming efficiency, it is demonstrated that they have a difficulty in electrical erasing. As an example, the a-ITZO TFT memory cannot show the shift of V th to the negative bias even with negative biasing from −10 to −30 V for 1 ms. 36 This is because the SiO x charge storage layer contains a number of traps including shallow and deep traps. During programming under a positive gate bias, the majority of electrons quickly drift from the conduction band of the ITZO active layer through the tunneling layer and are trapped in the forbidden gap of the SiO x layer.…”

“…LAYER To date, various AOS films have been explored for TFT memory devices, including a-IGZO, InSnZnO (ITZO), 36,38,61 ZnSnO, 62 and Hf-doped ZnO. 25,63 Most of them were prepared by the solution process and magnetron sputtering.…”

“…With respect to trap-rich dielectric-based charge-trapping layers, various dielectrics have been examined in oxide semiconductor TFT memories, such as SiO x , SiN x , HfO 2 , ErTi x O y , Ta 2 O 5 , Zn-doped Al 2 O 3 , defect-engineered alumina dielectric, and TiAlO, whose fabrication methods include plasma chemical vapor deposition (PCVD), reactive sputtering, spin-coating, and ALD. ,,,− Yi’s group used an inductively coupled plasma chemical vapor deposited SiO x (Si-rich SiO x ) film as a charge storage layer for a-IGZO and amorphous InSnZnO (a-ITZO) TFT memories. , Although both of the memories show a high programming efficiency, it is demonstrated that they have a difficulty in electrical erasing. As an example, the a-ITZO TFT memory cannot show the shift of V th to the negative bias even with negative biasing from −10 to −30 V for 1 ms . This is because the SiO x charge storage layer contains a number of traps including shallow and deep traps.…”

“…Therefore, it is strongly desired to reduce defects in the insulating layers as much as possible. So far, various dielectrics have been investigated as the tunneling and blocking layers for oxide semiconductor TFT memories, such as Al 2 O 3 , ,,, SiO 2 , ,− SiO x N y , , HfO 2 , and AlTiO x . The involved methods include ALD, dry oxidation, sputtering, plasma-enhanced chemical vapor deposition (PECVD), etc.…”