High Performance PCM&DRAM Hybrid Memory System

Abstract

: In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

RSLSP: An Effective Recovery Scheme for Flash Memory Leveraging Shadow Paging

“…Return all rescue operations that aim to use accrued a few pages in the page map entry or reduce the block map entry technology to reduce page reads. Since the largest NAND flash memory processing block has another restriction, the page must be continuously programming from the first to the last page (so random page programming is strictly prohibited) blocks if the big memory block NAND [23]. If the large memory block NAND [24], although the largest NAND flash memory programming block presents another constraint, the page must be continuously programming from the first page to the last page (so, the random page programming is prohibited stringently) blocks.…”