High performance SHA-2 core using the Round Pipelined Technique

Rote, Manoj D; Vijendran, N; Selvakumar, David

doi:10.1109/conecct.2015.7383912

Cited by 19 publications

(15 citation statements)

References 4 publications

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“…Mestiri et al [35] optimized the SHA256 and SHA512 serial algorithms on the Xilinx Virtex-5 FPGA to improve the performance/area ratio. Rote et al [36] optimized the structure of each round operation of SHA256 and SHA512 through the round pipelined technique to increase the algorithm frequency. Michail et al [37], [38] aimed at the SHA1 and SHA2 series hash algorithms using a variety of FPGA optimization techniques to achieve high-throughput and area-efficient multimode architectures, which can support single-or multimode algorithms of SHA1, SHA256 and SHA512.…”

Section: B Password Recovery Algorithmmentioning

confidence: 99%

Reconfigurable and High-Efficiency Password Recovery Algorithms Based on HRCA

Feng

Chen

et al. 2021

IEEE Access

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Cryptographic algorithms are widely used in information security fields such as network protocol authentication and commercial encryption software. Password recovery based on the hash algorithm is an important means of electronic forensics, encrypted information restoration, illegal information filtering, and network security maintenance. The traditional password recovery system is based mainly on the CPU and GPU and has a low energy efficiency ratio and cracking efficiency and cannot meet highperformance computing requirements. To further improve the computational efficiency and application flexibility of password recovery algorithms, this paper proposes a reconfigurable computing kernel design method based on a hybrid reconfigurable computing array (HRCA). Through in-depth analysis of the hash algorithm, the basic computing kernel set is extracted, and the combination design is carried out from the unit kernel, interconnection and storage structure to reconstruct the hash algorithm to match the application with the appropriate structure. Second, combined with the pipeline technology, the full pipeline hash and high-speed password attack algorithms are optimized and implemented to meet the needs of highperformance computing. Finally, an advanced computing kernel library is established, and the combination of a computing kernel map from the control and communication levels to achieve multidimensional reconfigurable computing and an overall placement strategy is used to make full use of the chip resources to improve computational efficiency. The experimental results and analysis show that compared with traditional CPU and GPU methods, the password recovery algorithm designed in this paper has the highest cracking speeds at 78.22 times and 2.65 times that of the CPU and GPU, respectively, and the highest energy efficiency ratio is 25.88 times and 3.16 times that of the CPU and GPU, respectively. Furthermore, the recovery efficiency has been significantly improved and meets the requirements of high-performance password recovery computing.

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Section: B Password Recovery Algorithmmentioning

confidence: 99%

Reconfigurable and High-Efficiency Password Recovery Algorithms Based on HRCA

Feng

Chen

et al. 2021

IEEE Access

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“…As below, we separately discuss other implementations of SHA-256 circuit and other implementations of HMAC-SHA-256 circuit. 6.1.1 Scan-based Attack against Other SHA-256 Circuit Implementations As far as we know, basic iterative SHA-256 circuit [29], [40], two-unrolled SHA-256 circuit [41], [42], pipelining SHA-256 circuit [43], [44], two-unrolled pipelining SHA-256 circuit [45], four-unrolled pipelining SHA-256 circuit [45], and compact SHA-256 circuit [46] are proposed as SHA-256 circuit implementations.…”

Section: Scan-based Attack Against Other Sha-256/hmac-sha-256 Circuitmentioning

confidence: 99%

“…When we can insert arbitrary messages into this SHA-256 circuit, we expect that STEP 2 and STEP 3 in the proposed method can be successfully applied to this circuit implementation. Pipelining SHA-256 circuit [43], [44] The pipelining implementation of the SHA-256 circuit processes PHASE 2 of Algorithm 1 in a pipelined manner. In this implementation, the processes on the left side (a partial circuit composed of the registers a, b, c and d) and the right side (a partial circuit composed of the registers e, f , g and h) in Fig.…”

Section: ]mentioning

confidence: 99%

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

Oku

Yanagisawa

Togawa

2018

IPSJ Transactions on System LSI Design Methodology

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Abstract:A scan chain is used by scan-path test, one of design-for-test techniques, which can control and observe internal registers in an LSI chip. On the other hand, a scan-based side-channel attack is focused on which can restore secret information by exploiting the scan data obtained from a scan chain inside the crypto chip during cryptographic processing. In this paper, we propose a scan-based attack method against a hash generator circuit called HMAC-SHA-256. Our proposed method is composed of three steps; Firstly, we isolate 64 bit-transition groups from a scan data using scan signatures based on the property of the HMAC-SHA-256 algorithm. Secondly, we classify these 64 bittransition groups into 32 pairs. Lastly, we find out the correspondence between the scan data and the internal registers in the target HMAC-SHA-256 circuit. Our proposed method restores the secret information by the three steps above, even if the scan chain includes registers other than the target hash generator circuit and hence it becomes too long. Experimental results show that our proposed method successfully restores two secret keys of the HMAC-SHA-256 circuit using up to 425 input messages in 7.5 hours.

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“…From a hardware perspective, [7]- [22] proposed solutions to improve SHA-256. For instance, the authors of [7] employed the carry-save adder to improve the computation time of the critical path, which increased the maximum frequency and processing rate, while [8]- [12] used pipeline technology to improve the SHA-256 throughput. A cache memory technique was presented in [13] to reuse data, minimize the critical paths, and reduce the number of memory accesses for SHA-256 processing.…”

Section: Introductionmentioning

confidence: 99%

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

et al. 2020

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In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18 µm technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5.9mm×5.9mm, and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

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High performance SHA-2 core using the Round Pipelined Technique

Cited by 19 publications

References 4 publications

Reconfigurable and High-Efficiency Password Recovery Algorithms Based on HRCA

Reconfigurable and High-Efficiency Password Recovery Algorithms Based on HRCA

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

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