High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

Sung, Po-Jung; Cho, T.-C.; Chen, P.-C.; Hou, Fu-Ju; Lai, Chao-Hung; Lee, Y.-J.; Li, Y.; Samukawa, Seiji; Chao, Tien−Sheng; Wu, Wen−Fa; Yeh, Wen–Kuan

doi:10.1109/nano.2016.7751473

Cited by 2 publications

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“…The channel material composition also influences the threshold voltage sensitivity to the temperature: considering silicon, gallium arsenide, indium arsenide, and indium phosphide, the minimum and maximum threshold voltage variations were observed for indium arsenide and silicon, respectively [37]. It is possible to use strain technology in order to further increase the device performance; a layer of SiN is deposited and, depending on the deposition conditions, the strain could be compressive or tensile [36]. The figures of merit of reported junctionless GAAFETs are presented in Table 1.…”

Section: Gate-all-aroundmentioning

confidence: 99%

“…This device turned out to be the first one of a new generation of transistors. In the last decades, many other junctionless devices were proposed, which includes FinFET , Gate-All-Around (GAA) [24][25][26][27][28][29][30][31][32][33][34][35][36][37], Single Gate (SGJLT) [38][39][40][41][42][43][44][45][46][47][48][49][50], Double Gate (DGJLT) , Thin Film (TFT) [76][77][78][79][80][81][82][83][84][85][86], and Tunnel FET (TFET) [87][88][89][90][91][92][93][94][95][96][97]. Because most of the review papers on JLTs were published in 2010-2014…”

Section: Introductionmentioning

confidence: 99%

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Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Gate-all-aroundmentioning

confidence: 99%