High Performance Silicon Nanowire Field Effect Transistors

Abstract

Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V‚s with peak values of 2000 nS and 1350 cm 2 /V‚s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.Semiconductor nanowires (NWs) [1][2][3][4][5][6] and carbon nanotubes (NTs) 7-12 are attractive components for future nanoelectronics since they can exhibit a range of device function and at the same time serve as bridging wires that connect to larger scale metallization. For example, field effect transistors (FETs) have been configured from NWs 1,3,4 and NTs 7-11 by depositing the nanomaterial on an insulating substrate surface, making source and drain contacts to the NW or NT ends, and then configuring either a bottom or top gate electrode (Figure 1). This basic approach may serve as the basis for hybrid electronic systems consisting of nanoscale building blocks integrated with more complex planar silicon circuitry, although a number of issues including device performance, reproducibility, and integration will have to be addressed in order to realize such systems in the future.In the case of NT FETs, considerable effort has been placed on improving key device parameters such as the carrier mobility and transconductance. For example, recent studies reported by Avouris and others [9][10][11][12] have shown that the measured carrier mobility can be increased significantly by contact thermal annealing. The fact that NT samples consist of mixtures of semiconducting and metallic building blocks could, however, represent a hurdle to future developments in nanoelectronics. 13 On the other hand, silicon nanowires (SiNWs) are always semiconducting, and the dopant type and concentration can be controlled during synthesis. 1 SiNW building blocks may also be more readily integrated into silicon industry processing and fabrication than NTs, 14 and thus might reduce barriers to the creation of hybrid structures. Initial transport studies of SiNW FETs showed relatively low transconductance and carrier mobility (∼0.01 cm 2 /V s). 1 Subsequent investigations of SiNW transistor characteristics in a crossed NW FET configuration 4 indicated that the initial low transconductance and mobility values were due in part to poor contacts between the SiNWs and source-drain electrodes and are not intrinsic...

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