High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology

Cho, Myung Kwan; Kim, D.M.

doi:10.1109/55.852963

Cited by 77 publications

(12 citation statements)

References 8 publications

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“…Recently, however, the NAND Flash memory industry has faced the scaling limitation of the conventional floating gate (FG) NAND cell. For a promising solution as the alternative technology to replace FG flash memory, the charge trap type flash memory, like Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been focused since it provides simpler process steps than FG [3], lower cell-to-cell coupling [4], and virtual immunity to stress-induced leakage current (SILC) [5].…”

Section: Introductionmentioning

confidence: 99%

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Kim¹,

Yang²,

Kim³

et al. 2015

Transactions on Electrical and Electronic Materials

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This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) siliconoxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

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Section: Introductionmentioning

confidence: 99%

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Kim¹,

Yang²,

Kim³

et al. 2015

Transactions on Electrical and Electronic Materials

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“…Metal-oxide-nitrideoxide-semiconductor (MONOS) memory devices have simple structures and great potential for low programming power and scalability, [1][2][3] making them promising candidates to replace existing forms of flash memory. MONOS memory devices operate according to a variety of principles, including Fowler-Nordheim (F-N) injection, [4][5][6] channelhot-electron (CHE) injection [7][8][9] and source-side hot-electron injection. [10][11][12][13] F-N injection is not suitable for applications that require high-speed and low-voltage programming.…”

Section: Introductionmentioning

confidence: 99%

Novel 2-Bit/Cell Metal–Oxide–Nitride–Oxide–Semiconductor Memory Device with Wrapped-Control-Gate Structure That Achieves Source-Side Hot-Electron Injection

Tomiye¹,

Terano²,

Nomoto³

et al. 2005

Jpn. J. Appl. Phys.

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We have proposed a novel 2-bit/cell metal-oxide-nitride-oxide-semiconductor memory device with a wrapped gate. Programming and erasing operations are performed by source-side hot-electron injection and hot-hole injection, respectively. Programming speeds of less than 1 ms, programming currents of less than 0.2 mA/mm, and erasing speeds of 10 ms were achieved. In this paper, we describe the abilities of this device and the mechanism of the operation by using a device simulator.

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“…The over‐erase is the critical fault mechanism since the NOR memory cells are connected parallel to a corresponding sense amplifier. [ 58 ] In the over‐erase case, too much hole h trapping induces the V th < 0 V, causing sneak current flow through unselected cells.…”

Section: Cell Array Architecture: Nor Versus Nandmentioning

confidence: 99%

Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology

Cited by 77 publications

References 8 publications

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Novel 2-Bit/Cell Metal–Oxide–Nitride–Oxide–Semiconductor Memory Device with Wrapped-Control-Gate Structure That Achieves Source-Side Hot-Electron Injection

Review of Semiconductor Flash Memory Devices for Material and Process Issues

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