High performance TLM simulation using adjustable time steps

Abstract

This work presents a novel numerical scheme for the acceleration of the 2-D Transmission-Line Matrix method. The idea is the use of contmlled leaps in the lime step in order to achieve faster processing. The leaps are numerically stable and may result in significant CPU savings. In addition to the adjustable time step, the procedure becomes more efficient by using model reduction with Schur decomposition. The technique was validated by the calculation of a microwave filter and subsequent comparison to the normal TLM results.Index Terms -CAD tools, Numerical Techniques, ModelReduction. IN~RODIICTIONThe TLM method (Transmission-Line Matrix) is a numerical technique applied to the general solution of the Maxwell equations. The problem is usually solved in the time domain using transmission line network analogies. Thc method can solve complcx and arbitrary shaped problems. However, TLM is also hound hy the same limitations of other numerical techniques. For instance, if one uses TLM to perform a n electromagnetic analysis of microelectronic circuits, the method will show several drawbacks. In this particular case, due to the relationship of the spatial and temporal discretization, a TLM analysis of an integrated circuit system demands large amounts of memoq. Moreover, the solution will require several millions of time steps. As a result, a full electromagnetic simulation of such a system is often impractical. This work presents an improvement in the TLM method to overcome the problems shown above. The authors of this article would like to suggest the name Johns Super Node (TLM-JSN) for the technique. This is a tribute to the creator of this method, P. B. Johns et al. [I]. The new formulation allows significant CPU savings for simulations. The theory describing TLM-JSN and the model reduction technique (ROW arc shown in the next section. The final section shows some examples that are compared to [2]-[31. 11. THEORY The electromagnetic waves in the TLM method propagate through a mesh of transmission lines interconnected at the nodes [4]. This process is described as a function of an incident and reflected vologe waves, v' and V', respectively at the nodes. As demonstrated in [21, the algorithm may he expressed by the interactive resolution of: [VI; =[SI. [VI. Where [SI is the scattering matrix that refers to the mesh nodes, and [C] is the connection matrix that describes the network's topology. In (1) and (2). k and kcl indicate the discretized time step in which the incident and reflected voltages are calculated. The TLM-JSN uses a state equation formulation to relate the incident and the reflected voltages. In the JSN method, the problem is divided into outer and inner domains. The solution is based on the calculation of the extemal reflected voltage in the outer domain ,V'caused by the incident voltages in the inner domain ,nv' and the incident voltages from the extemal domain_V'. Therefore, ( I ) and (2) are formulated as an interactive sequence:(4)Where [SI and [C] are the same matrices as in (I) and(2). [TI is t...

RF CMOS Device Modelling for on Chip EMC Evaluation

“…The results achieved using this infrastructure for the same NMOS_1 are presented on Figure 8 The following step on the proposed methodology is the calculation and insertion of EMI in test cells (CMOS inverter amplifier and NAND logical gate, presented on Figure 9). The basis used for this task was the CAD for electromagnetic field cartography mentioned before (5,19). To calculate the coupling capacitances, the CAD mentioned on EMI and EMC subject (17) was used.…”

“…The next step for this work is to simulate the chosen circuits with the interferer signal coupling at different points in the circuit, for example at the bias lines. A CAD tool that will integrate the data generated on the electromagnetic field amplitude CAD (19) with device, noise and EMC models is going to be developed in a near future. In this way, it will be achieved a computational tool able to analyze both sides of an IC projectschematics on circuit level and layout -considering EMC.…”

“…A computational tool has been developed (19) to create maps of electromagnetic field amplitude, from a given signal source, over a chip layout. This tool will be used together with the proposed models for active devices in circuits chosen to validate the response to EMI in a place on the SOC's layout.…”