High Performance Tri-Gate Germanium-on-insulator Based Junctionless Nanowire Transistors

Abstract

We fabricated high performance junctionless nanowire transistors (JNTs) directly on ultrathin-body Ge-on-insulator (GOI) substrates using a simple Si-compatible process. We reported the detailed fabrication process employing both optical lithography (OL) and electron beam lithography (EBL) to reduce costs and improve efficiency. These JNTs have gate lengths and channel widths that are both less than 100 nm and exhibit good electrical properties. The JNT with W/L=40 nm/70 nm, Na=1018 cm-3, and Ge-thickness dGe= 10 nm has Ion/Ioff ratio of approximately 105 at Vd=-1 V. The subthreshold slope and the drain-induced- barrier lowering (DIBL) are estimated to be 110 mV/dec at Vd=-0.1 V and 140 mV/V, respectively. The influence of Ge film thickness and temperature on electrical properties of these JLTs were investigated. Finally, we extracted the mobility of these JNTs and a peak mobility larger than 200 cm2V-1s-1 was observed.