High performance two-stage charge-pump for spur reduction in CMOS PLL

Park, Jungwoong; Kim, Namsoo; Jeong, Hyeim; Won, Da-sol; Choi, Ho Cheol

doi:10.1109/ssd.2014.6808749

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…Any change of that voltage results in frequency offset. [5,13,14]. In this regard, it is imperative to design a charge pump circuit that can generate a steady output current and can produce a superbly matched current with zero error in CPPLL.…”

Section: Introductionmentioning

confidence: 99%

Nano CMOS Charge Pump for Readerless RFID PLL

Badal

Reaz

Bhuiyan³

2019

Informacije MIDEM

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Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLL) is among the most crucial functional block in the Readerless RFID where the PLL performance greatly depends on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. To overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintains the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V, and the core occupies 17 x 59.5 μm2. The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performance.

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Section: Introductionmentioning

confidence: 99%

Nano CMOS Charge Pump for Readerless RFID PLL

Badal

Reaz

Bhuiyan³

2019

Informacije MIDEM

View full text Add to dashboard Cite

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“…The drain voltage of transistor MP3, MP4, MN3 and MN4 are forced to be the same by the operational amplifier. While the current mismatch caused by short channel length effect can be significantly reduced with adoption of the operational amplifier, the variation of the charge pump current with VCP_OUT still remains[16] [17]. The variation of charge pump current causes loop dynamics to vary with different output frequencies and PVT corners[18].…”

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confidence: 99%