High Power and High Frequency CMOS Oscillator With Source-to-Drain Coupling and Capacitive Load Reduction Circuit

Abstract

The proposed oscillator can increase the output power by coupling the signal at the source of the core transistor to the drain of the buffer transistor. In addition, the source-to-drain coupling generates an optimum negative transconductance at the desired operating frequency. A capacitive load reduction circuit is also applied to increase the fundamental oscillation frequency. Using these techniques, the fundamental and pushpush oscillators were implemented using 65 nm CMOS technology. The measurement results of the fundamental and push-push oscillators showed 2.7 and −25 dBm of peak differential output power at 194 and 394 GHz, respectively. In the 200 GHz frequency band, the proposed fundamental oscillator shows the highest output power among recently reported state-of-the-art CMOS oscillators.

Low phase noise buffer‐reused BiCMOS oscillator

“…4,5 The amplified buffer output signal is magnetically feedback from drain of cross-coupled FET, to source of cross-coupled FET in the core-oscillator to add negative transconductance in order to improve the startup condition for oscillator. 6 This should not be considered as buffer-feedback oscillator because it uses additional buffer pair for measurement purpose. The buffer-feedback oscillator in 7 uses a similar feedback technique reported for dualtank oscillators, implemented diversified cross-coupled architecture.…”