High power chip stacks with interleaved heat spreading layers

Abstract

3-D chip packaging and optoelectronic array interconnect technologies can be combined to realize ultra-compact hardware solution to systems requiring fast processing and handling of large data arrays. Thermal management is becoming a key issue if the active volume is minimized. The use of CVD diamond layers as a thermal management tool for the implementation of 3D stacks has been demonstrated to allow up to 80 W power dissipation in densely packed stacks of less than 1 cm3. IntroductionWhen manipulation and processing of large data arrays is required in image processing and recognition applications, existing planar silicon packaging based system implementations appear to be inadequate. As the size of the data arrays increase, it becomes difficult to pack the required processing units and sufficient memory within one single chip to carry out the required computation at high speeds due to the low yield for large silicon areas. On the other hand, the use of parallel hardware with many chips is not promising due to large areas resulting &om conventional packaging techniques which increases delay and power required to support the communication between chips. New hardware solutions capable of performing at high speeds are critically needed for the implementation of real time and adaptive signal processing systems. For example, if such image processing operations were performed on 1024x1024 data arrays with 32 bit accuracy at video rates, significant improvements could be obtained in electronic warfwe and industrial control applications.One way of packing more silicon circuits into a smaller volume is to use 3-D packaging techniques by stacking electronic chips. This packaging approach has the potential to significantly reduce the interconnection length of the intrachip connections within parallel processing groups. Since inter-chip distance is minimized, delay and power performance of the assembly is increased due to reduced system area (or volume). However, the reduction in system volume comes at the expense of heat extraction from the 3-D stacks. New thermal management approaches are needed to dissipate large amount of power in small volumes.

Impact of the number of chips on the reliability of the solder balls for wire-bonded stacked-chip ball grid array packages

“…The stacked chip package structure is designed to include more than one chip, so the thermal management of such packages has become very important, and some efforts have been made to yield solutions, by both experimental and simulation analyses [9][10][11][12][13][14][15][16]. The reliability of stacked chip packages is another subject to be addressed.…”

Direct liquid cooling of a stacked MCM

“…Massit and Nicolas [12] studied the thermal performance of a 3D module with a stack of 7 elementary silicon substrate modules, air cooling was used for the heat dissipation from the chips. Ozguz et al [13] investigated the use of diamond layers for thermal management in the 3D stacks. In their study, diamond heat spreader layers were added to each stacked chip to remove internally generated heat to the ambient environment.…”