High Pressure Deuterium Annealing Effect on Nano-Scale Strained CMOS Devices

Cho, Sung-Man; Lee, Jeong‐Hyun; Chang, Man; Jo, Minseok; Hwang, Hyunsang; Lee, J.-K.; Hwang, Sung Bo; Lee, Jong-Ho

doi:10.1109/relphy.2007.369564

Cited by 1 publication

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“…The additional neutron mass of D 2 makes less energy transfer; it is difficult to break the Si-D bond compared with Si-H [25]. Therefore, D 2 annealing has shown the improvement of the hot carrier effect, negative bias temperature instability (NBTI), threshold voltage (V T ) shift and so on [25][26][27][28]. In recent devices, such as FF, the improvement of reliability has been reported by high-pressure deuterium annealing (HPDA) [29].…”

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confidence: 99%

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

et al. 2020

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In this work, we studied the effect of high-pressure deuterium annealing (HPDA) on a p-type omega-gate nanowire field effect transistor by random telegraph noise (RTN) signal analysis. After HPDA under conditions of 400 • C and 10 atm for 30 min, I OFF decreases by 41.2% and I ON increases by up to 5.4%. Also, subthreshold swing (SS) is reduced from 72 mV dec −1 to 70 mV dec −1 . In RTN analysis, multi-level RTN is reduced to single-level RTN due to the passivation of a fast trap site by HPDA. ∆I D /I D is also decreased 1.3 and 1.1 times at |V OV | = 0.2 V and 0.4 V, respectively. From the low-frequency noise analysis, the reduction of trap density is observed by 86% at |V OV | = 0.4 V after HPDA. Through these results, we found that the HPDA reduces traps of gate dielectric and improves the quality of the interface between gate dielectric and NW channel in p-type OGNW FET.

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