High pressure deuterium annealing effect on nano- scale CMOS devices with different channel width

Cho, Sung-Man; Lee, Jeong-Hyn; Chang, Man; Jo, Minseok; Hwang, Hyunsang; Lee, J.-K.; Lee, Jong-Ho

doi:10.1109/nmdc.2006.4388705

Cited by 2 publications

(1 citation statement)

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“…Low-frequency noise analysis was also reported on the impact of HPDA for other device structures such as thin-film transistors and CMOS devices [30,31]. However, direct results on RTN affected by HPDA have not been obtained yet.…”

Section: Introductionmentioning

confidence: 99%

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

et al. 2020

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In this work, we studied the effect of high-pressure deuterium annealing (HPDA) on a p-type omega-gate nanowire field effect transistor by random telegraph noise (RTN) signal analysis. After HPDA under conditions of 400 • C and 10 atm for 30 min, I OFF decreases by 41.2% and I ON increases by up to 5.4%. Also, subthreshold swing (SS) is reduced from 72 mV dec −1 to 70 mV dec −1 . In RTN analysis, multi-level RTN is reduced to single-level RTN due to the passivation of a fast trap site by HPDA. ∆I D /I D is also decreased 1.3 and 1.1 times at |V OV | = 0.2 V and 0.4 V, respectively. From the low-frequency noise analysis, the reduction of trap density is observed by 86% at |V OV | = 0.4 V after HPDA. Through these results, we found that the HPDA reduces traps of gate dielectric and improves the quality of the interface between gate dielectric and NW channel in p-type OGNW FET.

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Section: Introductionmentioning

confidence: 99%

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

et al. 2020

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Characterization and modeling of negative bias temperature instability in P-MOSFETs

Yang¹

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It has been the intent of this work to investigate negative bias temperature instability (NBTI) in p-MOSFETS with ultra-thin nitrided gate oxides experimentally and theoretically. A systematic study on NBTI has been carried out and the understanding of NBTI mechanism is further enhanced. Firstly, a simple NBTI characterization technique of measuring a single-point saturation drain current has been proposed to minimize the unfavorable NBTI recovery during measurement. With this method, the measurement time can be largely reduced. This method gives a closer-to-real threshold voltage shift and thus yields a more reliable power-law factor. Subsequently, since NBTI has become a key device reliability challenge for advanced CMOS technology nodes, an NBTI in-line test methodology has been developed to monitor NBTI during the device development phase. Moreover, NBTI recovery is experimentally examined, and a combined empirical model for NBTI recovery within the modulated measurement time frame has been proposed to describe the entire process of NBTI recovery in a wide time range. A comprehensive study on the modeling of NBTI has been conducted. An analytical reaction-diffusion (R-D) model within the framework of the standard R-D model has been developed. This model can well describe NBTI in a wide time scale covering the three regimes of reaction, transition and diffusion. A power-law factor of ~1 is experimentally observed for the nitrided gate oxide, which shows clear evidence of the existence of the reaction-limited regime for NBTI. The analytical R-D model

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High pressure deuterium annealing effect on nano- scale CMOS devices with different channel width

Cited by 2 publications

References 3 publications

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

Reduction of random telegraph noise by high-pressure deuterium annealing for p-type omega-gate nanowire FET

Characterization and modeling of negative bias temperature instability in P-MOSFETs

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