High-Pressure Deuterium Annealing Effect on Nanoscale Strained CMOS Devices

Abstract

High-pressure deuterium annealing was applied to nanoscale strained CMOS devices, and its effect was characterized in terms of charge pumping method, hot-carrier-induced stress, negative bias temperature instability stress, and 1/f noise for the first time. For the NMOS, the characteristics of both control and tensile-stressed NMOS devices were improved by annealing; in particular, tensile-stressed NMOS devices had more improved characteristics than the characteristics of control devices. However, for the PMOS, compressive-stressed PMOS devices particularly had more degraded characteristics compared with the characteristics of control PMOS devices.Index Terms-Charge pumping, CMOS, deuterium (D) annealing, high pressure, hot carrier stress, nanoscale, negative bias temperature instability (NBTI) stress, strained, 1/f noise.