High-quality operation binding for clustered VLIW datapaths

Lapinskii, V.; Jacome, Margarida F.; Veciana, Gustavo A De

doi:10.1145/378239.379051

Cited by 15 publications

(5 citation statements)

References 17 publications

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“…While not a heavily researched area, there has been some work on estimate-based approaches for clustering. Lapinskii et al [17] base their estimate off three major factors: the data transfer penalty, FU serialization penalty and bus serialization penalty. They use a local approach like BUG to minimize the data transfer penalties.…”

Section: Related Workmentioning

confidence: 99%

Region-based hierarchical operation partitioning for multicluster processors

2003

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Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectures is compiler support to effectively partition operations across the available resources on each cluster. In this work, we present a novel technique for clustering operations based on graph partitioning methods. Our approach incorporates new methods of assigning weights to nodes and edges within the dataflow graph to guide the partitioner. Nodes are assigned weights to reflect their resource usage within a cluster, while a slack distribution method intelligently assigns weights to edges to reflect the cost of inserting moves across clusters. A multilevel graph partitioning algorithm, which globally divides a dataflow graph into multiple parts in a hierarchical manner, uses these weights to efficiently generate estimates for the quality of partitions. We found that our algorithm was able to achieve an average of 20% improvement in DSP kernels and 5% improvement in SPECint2000 for a four-cluster architecture.

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Section: Related Workmentioning

confidence: 99%

Region-based hierarchical operation partitioning for multicluster processors

2003

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“…While it seems to work well for architectures which communicate only in one direction, the algorithm is not very effective for architectures which can both read from as well as write to the adjacent clusters. Partially motivated by this and partially by Lapinskii et al [2001], we thus bring in an additional iterative improvement phase, by performing a local search around this initial binding (steps 6 to 13).…”

Section: Bindingmentioning

confidence: 99%

“…We have separate schedulers for RF-to-RF type architectures and direct intercluster communication architectures. Although a few scheduling algorithms for clustered architectures have been reported in the literature, they are all specifically targeted toward RF-to-RF type of architectures [Desoli 1998;Lapinskii et al 2001;Sanchez and Gonzalez 2000]. Our scheduling algorithm again is a list scheduling algorithm with the distance of the node from the sink as the heuristic.…”

Section: Final Schedulingmentioning

confidence: 99%

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

Gangwar¹,

Balakrishnan

Kumar

2007

ACM Trans. Des. Autom. Electron. Syst.

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VLIW processors have started gaining acceptance in the embedded systems domain. However, monolithic register file VLIW processors with a large number of functional units are not viable. This is because of the need for a large number of ports to support FU requirements, which makes them expensive and extremely slow. A simple solution is to break the register file into a number of smaller register files with a subset of FUs connected to it. These architectures are termed clustered VLIW processors.In this article, we first build a case for clustered VLIW processors with four or more clusters by showing that the achievable ILP in most of the media applications for a 16 ALU and 8 LD/ST VLIW processor is around 20. We then provide a classification of the intercluster interconnection design space, and show that a large part of this design space is currently unexplored. Next, using our performance evaluation methodology, we evaluate a subset of this design space and show that the most commonly used type of interconnection, RF-to-RF, fails to meet achievable performance by a large factor, while certain other types of interconnections can lower this gap considerably. We also establish that this behavior is heavily application dependent, emphasizing the importance of application-specific architecture exploration. We also present results about the statistical behavior of these different architectures by varying the number of clusters in our framework from 4 to 16. These results clearly show the advantages of one specific architecture over others. Finally, based on our results, we propose a new interconnection network, which should lower this performance gap.

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“…In traditional clustered VLIW processors, the notion of clustering is applied to minimize the complexity of the register files (datapath clusters) [36], [37]. In recent years, this notion has also been applied to minimize the complexity of the front end (instruction fetch) in the form of multi-VLIWs [38], [39].…”

Section: Related Workmentioning

confidence: 99%

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors

Jayapala

Barat

et al. 2005

IEEE Trans. Comput.

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High-quality operation binding for clustered VLIW datapaths

Cited by 15 publications

References 17 publications

Region-based hierarchical operation partitioning for multicluster processors

Region-based hierarchical operation partitioning for multicluster processors

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors

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