High-quality SiN _x /p-GaN metal-insulator-semiconductor interface with low-density trap states

Abstract

We report on a high-quality p-GaN metal-insulator-semiconductor (MIS) capacitors with sharp interface morphology and the lowest interface trap density by using SiNx as the gate dielectric layer. Transmission electron microscopy and x-ray photoelectron spectroscopy (XPS) analysis revealed a high-quality interface morphology with the effective removal of carbon and oxygen impurities. Better than the interface properties of Al2O3, SiO2, and CaF2/p-GaN metal-oxide-semiconductor (MOS) or MIS capacitors, the capacitance-voltage measurements of SiNx/p-GaN showed negligible electrical hysteresis after a two-step surface pre-treatment, leading to the lowest trapped charge density of 5 × 1010 cm−2. The interface state density distribution was also reduced to be ~1–2 × 1012 cm−2 · eV−1 at Et–Ev = 0.2–0.45 eV and 3–5 × 1012 cm−2 · eV−1 near the valance-band edge after the treatments. The achievement of the high-quality MIS interface was attributed to the suppression of the Mg-Ga-O interfacial disordered layer by the effective surface treatments and oxygen-free deposition process, which was usually observed at Al2O3/p-GaN MOS interface.

Passivation of hole traps in SiO2/GaN metal-oxide-semiconductor devices by high-density magnesium doping

“…On the other hand, as for the forward sweeps of the low and medium samples, both the maximum capacitance and the gate voltage showed a discrepancy between the experimental and ideal values that became pronounced depending on the doping conditions, suggesting a change in the density and energy distribution of hole traps near the interface. On the basis of these findings and previous reports, [19][20][21][22][23][24][25][26] it can be concluded that rather than the UHPA process, 27) the concentration of Mg atoms and/or the Fermi level of the p-GaN substrate play a decisive role in the passivation of hole traps.…”

“…17,18) In contrast, there are few reports on p-type GaN MOS capacitors that had well-behaved capacitance-voltage (C-V ) characteristics. [19][20][21][22][23][24] Because of the significant number of hole traps located near the oxide/GaN interfaces, a large C-V hysteresis is usually observed for p-type MOS capacitors. 25) Even worse, the surface potential of GaN is pinned and an ideal amount of hole accumulation at the MOS interface hardly occurs regardless of the gate dielectric materials used.…”

Metal-Al2O3-GaN capacitors with an ultraviolet/ozone plasma-treated interface

“…Several methods were introduced to improve the surface quality of GaN, such as using interface passivation layers, wet cleaning, and plasma treatments. [14][15][16][17][18][19] It was reported that a thin layer of high-quality gallium oxide (Ga 2 O x ) formed by surface oxidation of GaN can function as a passivation layer due to its low interface trap states density. 4,14,20,21) In comparison to the high-temperature process and other methods used to form Ga 2 O x to improve surface quality, ultraviolet/ozone (UV/O 3 ) treatment is a multifunctional low-temperature and low-cost process that can be used for surface cleaning as well as surface oxidation without inducing surface damages.…”

Advanced atomic layer deposition: metal oxide thin film growth using the discrete feeding method

“…This implied that the DF-ALD improved HfO 2 /Si interface characteristics for the aforementioned reasons. 28–30…”

“…This implied that the DF-ALD improved HfO 2 /Si interface characteristics for the aforementioned reasons. [28][29][30] Fig. 3d shows the plot of CET vs. leakage current density ( J g ) of the MOS capacitors to examine the insulating characteristics of the HfO 2 films.…”