High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications

Jin, Xing; Chen, Weichong; Li, Ximing; Yin, Ningyuan; Wan, Caihua; Zhao, Mingkun; Han, Xiufeng; Yu, Zhiyi

doi:10.1109/tcsii.2022.3213747

Cited by 7 publications

(3 citation statements)

References 19 publications

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“…1(a), the SOT-MTJ device has three ports, where W1, W2 are write ports and R is a read port. The write and read paths are separated, which allows the MTJ resistance to be changed to the high level required by IMC by adjusting the tunnel barrier thickness without affecting the write [29], and also avoids the interference of false writes caused by the spin-transfer-torque MTJ (STT-MTJ) when reading data because the read and write operations share a path [30,31]. MTJ has good compatibility with CMOS process, and it can be deposited onto CMOS in the back-end process, as shown in Fig.…”

Section: Sot-mtj Devicementioning

confidence: 99%

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Jin

Yin

Chen

et al. 2023

IEICE Electron. Express

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Traditional von Neumann architecture bottlenecks such as the "memory wall" limit artificial intelligence (AI) development, and inmemory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

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Section: Sot-mtj Devicementioning

confidence: 99%

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Jin

Yin

Chen

et al. 2023

IEICE Electron. Express

Self Cite

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“…The PSNR value of this scheme is 80%. X. Jin et al, [4] proposed an 8-bit non-volatile full adder with the method of magnetic tunnel junction for image processing application of gaussian filter. A. Sadeghi et al, [5] implemented an approximation computing technique with the help of a full adder with 12 transistors and ripple carry adder for many image processing applications but does not mention lowpower energy techniques.…”

Section: Background Workmentioning

confidence: 99%

Low Power Adders for Efficient Image Processing Applications

L.Sowmiya,

Ramesh SM,

Arul A

et al. 2023

Int Res J Adv Engg Hub

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In the world of digitalization, low-power circuits are necessary for building fast operating processors. Additionally, low-power circuits consume less energy and the lifetime of the electronic devices can extended to the maximum. Adders are significantly used in digital image processing techniques and for many Very Large-Scale Integration (VLSI) applications. Due to this, demand for creating efficient adders has become high in recent years. Using approximate adders is much more convenient than exact adders and the results of approximation adders are better than exact adders. Approximation adders can be executed for many signal-processing applications and are mainly considered for image-processing applications. SESA and SEDA are very good in providing efficiently lower energy when compared to other mirror adder circuits and are cost-efficient. Improvements and further extensions of the proposed model can easily make for building efficient microprocessor chips and these adders are used in next-generation electronic devices.

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“…Thus, they do not harness the full benefits of MTJ, and the power and area of such circuits are exacerbated while extending to multiple bits/inputs. These issues are addressed in [45], [48], [49], where fully non-volatile full adders with MTJs as part of the logic tree performing computation. However the crisscross arrangement and series connection of MTJs in these designs induce complexity in the writing process as a single write circuit will not suffice to write different input values, thus increasing write power and area.…”

Section: Related Workmentioning

confidence: 99%

A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic

Rangaprasad,

Joshi

2023

IEEE Access

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Spintronics has been garnering great success in resolving the shortcomings of conventional charge-based electronics and von-Neumann architecture by offering novel computational paradigms almost devoid of leakage effects and volatility issues of traditional CMOS systems. Especially, hybrid CMOS/MTJ circuits integrating all benefits of spintronics with well-evolved CMOS technology have been extensively investigated as candidates for building next-generation processors. Motivated by the importance of magnetic processors, in this work, a novel fully non-volatile reconfigurable magnetic arithmetic logic unit (NVR-MALU) based on majority logic has been proposed. This paper encompasses the prospects of NVRMALU at both the architecture level and circuit level by discussing multi-context hybrid CMOS/MTJ LIM architecture and operation of the circuit. Furthermore, the simulation results of the proposed fully non-volatile reconfigurable magnetic full adder (NVRMFA) making up NVRMALU reveal a remarkable total power reduction by around six to forty-seven folds compared to its contemporary magnetic full adders (MFAs) discussed here. Also, NVRMALU is superior to double pass transistor clocked CMOS (DPTLCMOS) ALU in terms of power reduction by six times, thus qualifying it as an excellent normally OFF, Instant ON digital system. A four-bit extension of NVRMALU has been presented as a sign of the feasibility of the design for multi-bit applications. The transient analysis demonstrates nonvolatile and dynamic reconfigurable traits of NVRMALU in addition to functionality verification. Additionally, variability analysis has been performed to study the factors controlling read and write performances of hybrid circuits from a device-level perspective.

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High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications

Cited by 7 publications

References 19 publications

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Low Power Adders for Efficient Image Processing Applications

A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic

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