High-resistivity silicon-based substrate using buried PN junctions towards RFSOI applications

Moulin, Maxime; Rack, Martin; Fache, T.; Chalupa, Zdenek; Plantier, Christophe; Morand, Y.; Lacord, J.; Allibert, F.; Gaillard, F.; Lugo, J.; Hutin, Louis; Raskin, J.-P.

doi:10.1016/j.sse.2022.108301

Cited by 7 publications

(2 citation statements)

References 13 publications

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“…The metallisation layers used correspond to a metal level and a thick copper layer, equivalent to usual top Aluminium metal in terms of resistivity. In order to reduce the PSC, underneath some devices, we implanted alternatively P and N, so that the PN patterns follow the metallisation loop, as proposed in [2]- [4]. The implants are designed to reach approximately the same depth and concentration of dopants.…”

Section: Fabrication Of the Devicesmentioning

confidence: 99%

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Buried PN Junctions Impact on the Performances of an Inductor at RF Frequencies

Fache

Moulin

Charlet

et al. 2023

2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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Section: Fabrication Of the Devicesmentioning

confidence: 99%

“…Said layer is called parasitic surface conduction (PSC) [1]. New integration techniques were implemented in order to obliterate this parasitic feature, such as buried PN junctions [2]- [4], which is the alternative explored in this article. This integration is compatible with SOI substrate, in zones where the SiO 2 Box is removed locally.…”

Section: Introductionmentioning

confidence: 99%

Buried PN Junctions Impact on the Performances of an Inductor at RF Frequencies

Fache

Moulin

Charlet

et al. 2023

2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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Defect Engineering for Enhanced Silicon Radiofrequency Substrates

Perrosé,

Baron,

Lefaucher

et al. 2024

Physica Status Solidi (a)

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Herein, high‐resistivity silicon substrates with specific He+ ion implantations to mitigate the parasitic surface conduction effect are studied. Several postimplantation thermal annealing conditions are investigated. Substrate performance is assessed at radiofrequencies (RFs) using the small‐signal characterization of coplanar waveguides (CPW) structures. The best effective resistivity (ρeff) of 4 kΩ cm is achieved with the wafer annealed at 600 °C for 2 h. This ρeff value is also stable as a function of DC bias applied to the CPWs. Those high RF performances originate from the nature of the defects created by ion implantation. Defects are deeply analyzed using spectroscopy measurement and scanning transmission electron microscopy. Combining these measurements, it is shown that {311} defects are probably responsible for the achieved high RF performances. Finally, the link between charge carriers trapping in the RF domain and defects nature is discussed to develop a defects engineering strategy for low‐loss RF substrates. The proposed fabrication method enables the fabrication of RF passivation layer locally over the wafer, and thus the cointegration of RF devices with fully depleted silicon‐on‐insulator technology.

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