High resolution nanotopography characterization at die scale of 28nm FDSOI CMOS front-end CMP processes

Dettoni, Florent; Rivoire, M.; Gaillard, S.; Hinsinger, O.; Bertin, F.; Beitia, C.

doi:10.1016/j.mee.2013.08.001

Cited by 11 publications

(5 citation statements)

References 1 publication

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“…Fig. 3 shows two things that can be derived from offline reference topography measurement done on a Veeco WYKO NT9300 tool in LETI without the photolithography process stack [8]. The height distribution in field (in green) which is mainly spread between 45 and 75nm but presents some excursions of a few tens of nanometres in atypical areas of the chip and the best focus to topography correlation (in blue) which shows a slope close to 1with an excellent correlation factor.…”

Section: -The Topography Induced Focus Non-uniformitymentioning

confidence: 99%

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Verification and application of multi-source focus quantification

Simiz

Hasan²,

Staals

et al. 2016

SPIE Proceedings

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Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx Proc. of SPIE Vol. 9781 97810S-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx Proc. of SPIE Vol. 9781 97810S-3 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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Section: -The Topography Induced Focus Non-uniformitymentioning

confidence: 99%

“…These were done on a Veeco WYKO NT9300 tool in LETI without the photolithography process stack [8]. A topography model was constructed using a partial least square linear prediction method by combining GDS densities of the underlying layers.…”

Section: -Modelling Topography With Gds Densitiesmentioning

confidence: 99%

Verification and application of multi-source focus quantification

Simiz

Hasan²,

Staals

et al. 2016

SPIE Proceedings

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“…Most of these areas are not expected to be present on a product but are necessary for the development of a technology. The topography measurements were done a Veeco WYKO NT9300 tool in LETI without litho stack [7]. The measurements allow a mapping of one field with pixels of a few µm².…”

Section: -Best Focus Vs Topography Analysismentioning

confidence: 99%

Product layout induced topography effects on intrafield levelling

et al. 2015

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International audienceWith continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 2, 5] show that even though the intrafield component stays the same, it becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. In a previous paper, the feasibility of anticipating the scanner levelling measurements (Level Sensor, Agile and Topography) has been shown [1]. This model, built using a multiple variable analysis (PLS: Partial Least Square regression) and GDS densities at different layers showed prediction capabilities of the scanner topography readings up to 0.78 Q² (the equivalent of R² for expected prediction). Using this model, care areas can be defined as parts of the field that cannot be seen nor corrected by the scanner, which can lead to local DOF shrinkage and printing issues. This paper will investigate the link between the care areas and the intrafield focus that can be seen at the wafer level, using offline topography measurements as a reference. Some improvements made on the model are also presented

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“…While this technique is very useful for a global view at the wafer scale, there is a need for a more accurate view at the die scale. At CEA Leti, we developed a methodology for full-die topography characterization by optical interferometry [5][6][7]. This technique allows us to acquire more than 50 million surface topography points and obtain an accurate image of the die-level topography, with a nanometric z-resolution and micrometric lateral (x, y) resolution.…”

Section: Introductionmentioning

confidence: 99%

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

Balan

Michel

Mendes

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nanotopography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.

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High resolution nanotopography characterization at die scale of 28nm FDSOI CMOS front-end CMP processes

Cited by 11 publications

References 1 publication

Verification and application of multi-source focus quantification

Verification and application of multi-source focus quantification

Product layout induced topography effects on intrafield levelling

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

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