High room temperature peak-to-valleycurrent ratio in Sibased Esaki diodes

“p-on-n” Si interband tunnel diode grown by molecular beam epitaxy

“…[1][2][3][4][5] The devices are particularly attractive for integration with Si-based microelectronic circuits and continued progress has seen the peak-to-valley current ratio ͑PVCR͒ exceed 5. The structure first demonstrated by Rommel et al 1 consists of diametrical n-and p-type ␦-doped layers separated by a narrow intrinsic barrier layer with similarities to an Esaki tunnel diode.…”

P and B doped Si resonant interband tunnel diodes with as-grown negative differential resistance

“…Discrete RITDs have been reported that have a peak-to-valley current ratio (PVCR) greater than 6 [1], peak current densities (PCD) greater than 218 kA/cm 2 [2], and voltage swings, V s , greater than 560 mV [3]. All of these devices have features in common: 1) the electron tunnelling occurs between bound states in the valence band and the conduction band created by highlydoped layers formed by d-doping; 2) a spacer layer between the two d-doped layers which includes Si 1-x Ge x to reduce the bandgap and reduce the out-diffusion of dopants from the B d-doped layer; 3) epitaxial growth at low temperature to reduce both the diffusion of dopants and the segregation of constituents during the growth; and 4) a post-growth anneal to reduce the effect of point defects which occur due to the low temperature epitaxial growth.In particular, room temperature RITD performance has been shown to be sensitive to Ge concentration [4], the width of the spacer layer [5] and to the temperature of the post-growth anneal [1,3,4]. In spite of the narrow process windows, SiGe RITDs have been successfully integrated with both complementary metal oxide semiconductor (CMOS) transistors [6] and heterojunction bipolar transistors (HBT) [7] to form elementary logic circuits.…”

“…In particular, room temperature RITD performance has been shown to be sensitive to Ge concentration [4], the width of the spacer layer [5] and to the temperature of the post-growth anneal [1,3,4]. In spite of the narrow process windows, SiGe RITDs have been successfully integrated with both complementary metal oxide semiconductor (CMOS) transistors [6] and heterojunction bipolar transistors (HBT) [7] to form elementary logic circuits.…”

Simplified Si resonant interband tunnel diodes

“…All of these devices, made by different research groups, have features in common: a) The electron tunneling occurs between bound states in the valence band and the conduction band created by highly doped layers formed by delta doping; b) a spacer layer between the two delta-doped layers which includes Si 1-x Ge x to reduce the bandgap and reduce the diffusion of dopants from the p-delta-doped layer; c) epitaxial growth at low temperature to reduce both the diffusion of dopants and the segregation of constituents during the growth; and d) a post-growth anneal to reduce the effect of point defects which occur due to the low temperature growth. In particular, the room temperature RITD performance has been shown to be sensitive to the Ge concentration [4], width of the alloy layer [5] and to the temperature of the post-growth anneal [4]. In spite of the narrow process windows, SiGe RITDs have been successfully integrated with both complementary metal oxide semiconductor (CMOS) transistors [6] and heterojunction bipolar transistors (HBT) [7] to form elementary logic circuits.…”