High-speed and High-efficient Modulo (2n-3) Multipliers

Abstract

Abstract-In this paper, an algorithm for designing efficient modulo 2n-3 multipliers is proposed. With this algorithm, we can design the fastest among all known modulo 2n-3 multipliers by applying some simple correction terms. Implemented using 90nm CMOS process technology, the proposed modulo 2n-3 multiplier can improve the current state of the art by 3.9% on the average in terms of area and 10.5-36.4% in terms of performance delay.