High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM

Yabe,; Matsuoka,; Satô,; Hayakawa,; Matsui,; Aono,; Yoshimura,; Ishimaru, K.; Gojohbori,; Morita,; Unno,; Kakumu,; Ochii,

doi:10.1109/vlsic.1993.920564

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Dynamic Threshold Voltage Control Concept1

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1995

2022

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“…In order to simultaneously achieve high performance during active periods and low leakage power during idle periods for burstmode computational systems, several schemes of reducing the leakage current have been proposed. The multiple CMOS design involves using high transistors to gate the low blocks [5], [6]. Both NMOS and PMOS transistors are needed in order to preserve state.…”

Section: Dynamic Threshold Voltage Control Conceptmentioning

confidence: 99%