High Speed and Wide Bandwidth Delta-Sigma ADCs

Bolatkale, Muhammed

doi:10.1007/978-3-319-05840-5

Cited by 14 publications

(12 citation statements)

References 2 publications

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“…The modulator's clock signal is generated by another signal generator (E8663B), which outputs a 640-MHz sinewave with 5 dBm of output power. 1 As with the input signal described above, the resulting single-ended signal is converted to a differential signal by a balun (0.4-800 MHz) and fed into the low-voltage differential signaling (LVDS) circuit, and the CLK IN and CLKB IN signals are generated by the LVDS output. The speed of the CT-DSM output and the CLK OUT should be reduced at a rate at which the logic analyzer (16801A) can accept using digital logic.…”

Section: Resultsmentioning

confidence: 99%

“…In the past, delta-sigma ADCs were used mainly to achieve high-resolution performance in low-frequency signal bandwidths; however, thanks to advances in process and technology, they have been extended to high-frequency bandwidths. 1 In particular, the continuous-time delta-sigma modulator (CT-DSM) architecture does not require an anti-alias filter design because the modulators possess inherent anti-aliasing. In other words, because it has the advantages of reducing chip area and power consumption, this architecture has been evaluated as a potential structure for applications in which power efficiency is important.…”

Section: Introductionmentioning

confidence: 99%

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A 20‐MHz bandwidth, 75‐dB dynamic range, continuous‐time delta‐sigma modulator with reduced nonidealities

Song

Lee

Roh

2019

Circuit Theory & Apps

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A 20-MHz bandwidth, 75-dB dynamic range, continuoustime delta-sigma modulator with reduced nonidealities Summary This letter presents a 4-bit continuous-time delta-sigma modulator (CT-DSM) fabricated using a 65-nm CMOS process. The circuit is designed for wide-bandwidth applications, such as those related to wireless communications. This CT-DSM has an oversampling ratio of 16 with a 640-MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn-to-zero (NRZ)-type pulse, whereas the second DAC pulse is a return-to-zero (RZ)-type pulse; this is accomplished using a current-steering DAC. In order to reduce mismatch without using a data-weighted averaging circuit, the size and layout of the unit current source in the current-steering DAC are considered carefully. The CT-DSM achieves a signal-to-noise ratio (SNR) of 67.3 dB, a signal-to-noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20-MHz signal bandwidth.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 20‐MHz bandwidth, 75‐dB dynamic range, continuous‐time delta‐sigma modulator with reduced nonidealities

Song

Lee

Roh

2019

Circuit Theory & Apps

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“…2, which mitigates the noise problem associated with the large bias current to some extent. In using the resistively degenerated PMOS current source technique, better matching and lower noise than a MOS only current source can be achieved [11]. By using a higher supply voltage of 1.8 V for the TIA, the degeneration resistance R S can be made relatively large to significantly reduce the noise contribution of I B .…”

Section: Tia Design and Implementationmentioning

confidence: 98%

A high resolution transimpedance amplifier for use in a 10-bit 200 MS/s current mode SAR ADC

Elkafrawy

Anders

Ortmanns

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2 GS/s and an overall Nyquist rate conversion speed of 200 MS/s. In this paper, the main focus is placed on the design of a high-resolution low-input-impedance transimpedance amplifier (TIA) used as the comparator preamplifier in the proposed current mode SAR ADC. The TIA converts the difference between the DAC feedback current and the output current of the input transconductance (Gm) stage to a voltage which is then quantized by a latch. For high-speed operation, trade-offs between input resistance, noise and voltage headroom pose challenges in the design of the high-speed TIA. More specifically, achieving a low input-referred noise current requires larger headrooms and thus higher supply voltages, which in turn reduces the TIA power efficiency. Thus, input impedance and input-referred noise current are the key determining factors for the design of high-speed TIAs in current based SAR ADCs. Our analysis is compared against a schematic level implementation in a 1.2 /1.8 V 90 nm CMOS technology. The TIA implementation is simulated on transistor level to achieve an overall resolution of 10 bit in the proposed current based SAR ADC together with the input Gm and current steering DAC over a Nyquist band from DC to 100 MHz.

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“…A well-known method is the time-interleaved analog-to-digital converter (ADC) that uses M parallel ADCs where each ADC samples data every M-th cycle of the effective sample clock. The result is that the sample rate is increased M times compared to what each individual ADC can manage [20,21]. According to the description above and using Eqs.…”

Section: Homodyne Ask Receiver With Ls Detectionmentioning

confidence: 99%

An efficient combining technique to analyze the performance of non-ideal ASK optical systems

Smadi

2015

Optics & Laser Technology

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High Speed and Wide Bandwidth Delta-Sigma ADCs

Cited by 14 publications

References 2 publications

A 20‐MHz bandwidth, 75‐dB dynamic range, continuous‐time delta‐sigma modulator with reduced nonidealities

A 20‐MHz bandwidth, 75‐dB dynamic range, continuous‐time delta‐sigma modulator with reduced nonidealities

A high resolution transimpedance amplifier for use in a 10-bit 200 MS/s current mode SAR ADC

An efficient combining technique to analyze the performance of non-ideal ASK optical systems

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