High speed Bias Temperature Instability measurements on 20nm RMG HKMG MOSFETs

Chandra, Nishant; Chandrashekhar, Sandhya; Francis, R.J.; Kerber, A.; Srinivasan, P.; Nigam, T.

doi:10.1016/j.sse.2014.06.032

Search citation statements

Order By: Relevance

Paper Sections

Select...

Methods1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2015

2023

Publication Types

Select...

Other1

Article1

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

(1 citation statement)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2. BTI stress was applied and measured under three stress voltages V G1 , V G2 and V G3 for at least ~1000 s using fast [7] and ultrafast [8] intermittent drain current sensing methodology. While fast sensing was performed with ~2 ms delay, ultra-fast sensing was carried at ~10μs delay.…”

Section: Methodsmentioning

confidence: 99%

NBTI in Si<inf>0.5</inf>Ge<inf>0.5</inf> RMG gate stacks — Effect of high-k nitridation

Srinivasan

Fronheiser

Siddiqui

et al. 2015

2015 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

Negative Bias Temperature Instability (NBTI) is assessed in (100)Si planar cSi 0.5 Ge 0.5 Replacement Metal Gate (RMG) gate stacks, with and without high-k nitridation for various post nitridation anneal (PNA) conditions. Observed initial N it was 8~9x10 11 cm -2 . Nitrided devices show higher NBTI than non-nitrided devices. Observed time slopes become shallower from ~0.25 to ~0.20. Overall, observed NBTI in cSi 0.5 Ge 0.5 stacks are promising making it viable for use in 7nm and below nodes.

show abstract

Section: Methodsmentioning

confidence: 99%