High-speed Booth encoded parallel multiplier design

Yeh, Wen-Chang; Jen, Chein-Wei

doi:10.1109/12.863039

Cited by 197 publications

(9 citation statements)

References 20 publications

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“…Generally, hardware multiplier adds partial products to complete the multiplication. For N-bit multiplication, there are N 2 partial products in the array multiplier [41]. When N becomes large, the adder tree will become complex, which subsequently increases area, time delay, and power consumption.Therefore, a growing number of novel algorithms like the Booth algorithm and optimized adder trees such as Wallace adder tree and Baugh-Wooley have been proposed to accelerate the multiplication speed.…”

Section: Booth Multipliermentioning

confidence: 99%

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

Zhu

Huang

et al. 2021

Electronics

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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Section: Booth Multipliermentioning

confidence: 99%

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

Zhu

Huang

et al. 2021

Electronics

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“…Fig. 2(c) depicts the contribution of spurious activities from both PPG and adder-tree of an 8-and 16-bit conventional Booth multipliers [27]. Note that these adder-trees were constructed utilizing full adders.…”

Section: B Spurious Activity Generationmentioning

confidence: 99%

“…The Booth multiplier has also been subjected to structural and gate-level optimizations in literature. A more regular partial product array [15], [16], [27] was proposed to minimize the extra adder rows for carry summation. The approach in [27] has improved the multiplier performance by 25% when compared with the conventional implementations.…”

Section: Introductionmentioning

confidence: 99%

“…A more regular partial product array [15], [16], [27] was proposed to minimize the extra adder rows for carry summation. The approach in [27] has improved the multiplier performance by 25% when compared with the conventional implementations. Kang and Gaudiot [15] presents a fast 2's complement generation circuit to reorganize the partial product array by removing the subsequent carry-in terms.…”

Section: Introductionmentioning

confidence: 99%

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Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

Ranasinghe

Gerez

2020

IEEE Trans. VLSI Syst.

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This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.

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“…We designed both conventional Booth multipliers and the proposed multiplier using Verilog HDL and verified the functionality for all the cases. The conventional Booth multiplier was designed in accordance with the study performed by Wen-Chang and Chein-Wei [7]. Each multiplier was built and optimized by Synopsys Design Compiler using CMOS libraries with constraints of maximum frequency in 32-nm processes by the Synopsys Armenia Educational Department.…”

Section: Methodsmentioning

confidence: 99%

Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm

Kim

Moon

Lee

2014

IEICE Electron. Express

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In this study, we propose a radix-16 Booth multiplier using a novel weighted 2-stage Booth algorithm. Most conventional multipliers utilize radix-4 Booth encoding because a higher radix increases encoder complexity. To resolve this problem, we propose the weighted 2-stage Booth algorithm. The synthesis results show that the multiplier using the proposed algorithm achieves better power-delay products than those achieved by conventional Booth multipliers. We believe that the proposed Booth algorithm can be broadly utilized in general processors as well as digital signal processors, mobile application processors, and various arithmetic units that use Booth encoding.

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High-speed Booth encoded parallel multiplier design

Cited by 197 publications

References 20 publications

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm

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