High Speed Energy Efficient Multiplier Using 20nm FinFET Technology

Vallabhuni, Rajeev Ratna; Saritha, M.; Saipreethi, N; Vijay, Vallabhuni; Shaker, P. Chandra; Divya, M.; Shaik, Sadulla

doi:10.2139/ssrn.3769235

Cited by 17 publications

(7 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…CPD for such kind of RCA adder restricts the speed of the framework. [1][2][3][4][5][6][7][8][9][10] A carry select adder (CSLA) is utilized to diminish this presentation metric, for example CPD. One of the productive plans to improve the speed of multi-bit adders is Square Root (SQRT)-CSLA.…”

Section: Introductionmentioning

confidence: 99%

CSA Implementation Using Novel Methodology: RTL Development

2023

VLSI

View full text Add to dashboard Cite

Carry Select Adder (CSLA) is an essentially utilized adder on account of its higher computational speed. CSLA is utilized in the space of incorporation frameworks. This paper proposes a CSLA design by carrying out the Logic Optimization Technique (ZFCLOT) using Zero Finding Logic contrasted with ordinary Zero Finding Logic (ZFC). This paper notices the different presentation measurements like area, power, delay, area delay product (ADP), power delay product (PDP) and effectiveness. Approval of the ZFCLOT put together CSLA is displayed with respect to Cadence stage utilizing 45 nm platform. The presented CSLA utilizing ZFCLOT has shown advanced execution measurements, explicitly, region and power improvement of 47.287% and 49.1%, separately contrasted with the current standard plans.

show abstract

Section: Introductionmentioning

confidence: 99%

CSA Implementation Using Novel Methodology: RTL Development

2023

VLSI

View full text Add to dashboard Cite

show abstract

“…The basic understanding of Adaptive filters is they try to equalize the random noise; if it can't equalize, they try to track the random statistics. [26][27][28][29][30][31][32][33][34][35] As noise is randomly occurred the coefficients change randomly, which results in increased complexity of the task for the filters. Some of the commonly used Adaptive filters are LMS and RLS.…”

Section: Introductionmentioning

confidence: 99%

Digital Filter based Adder Module Realization High-Speed Switching Functions

2023

VLSI

View full text Add to dashboard Cite

FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to implement any frequency response digitally. Usually, the FIR filters contain multipliers, adders and many delays. As we know, the number of MAC operations (multiply and accumulate) makes the FIR filter less efficient and increases hardware complexity. So in this project, we included DA (Distributed Arithmetic) architecture in designing the efficient adaptive FIR filter. The pipelined Distributive Arithmetic architecture provides less power, less area and high values of throughput in creating an adaptive FIR filter. These are used in Echo cancellations, Radio channel equalizers and speech coding. DA architecture also helps in improving the processing speed of the FIR filter by eliminating the number of multipliers. A reconfigurable filter design can be achieved with the help of this Distributive Arithmetic architecture. Here the sum of the partial products which is pipelined is passed as the input values, and it is stored in the LUT (lookup tables) of the distributive architecture. By replacing the adder of the shift accumulation unit with a carry-save adder, the area of the proposed design is reduced. By placing the ripple carry adder, the size and delay are reduced to a further extent. Here we will use the Xilinx ISE tool to verify the simulation result, area required and time consumed.

show abstract

“…In order to design high order IIR filter, filter stages of all pass filter, the delays and the masking filter methods. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] The frequency components of the input signals is allowed by the all pass filter which does not have any attenuation and the all pass filter will also provide different frequency of predictive phase shifts of the input signal. All Pass Filters are also named as Delay Equalizers or Phase Correctors.…”

Section: Introductionmentioning

confidence: 99%

“…[33][34][35][36][37][38][39] For example we can get the IIR Filter which is of high pass from the Low Pass IIR Filter. [18], [40] elays and the masking filter methods [15]- [32]. uency components of the input signals is allowed by the all pass filter not have any attenuation and the all pass filter will also provide different of predictive phase shifts of the input signal.…”

Section: Introductionmentioning

confidence: 99%

FPGA based Digital Filter Design for faster operations

2023

VLSI

View full text Add to dashboard Cite

The reduced complexity design of the IIR filter is discussed in this paper. The use of the IIR filter has been variably increasing during the present times and they are realtime applications. The filter complexity reduction is done to increase the usage of filters in FPGA. In this method, the coefficients are expressed in the form of 1's and 0's. The multiplied delays have been used which is used to scale down the complexity. Signal Flow Graph plays a critical role in identifying the difficult path. IIR Filter is programmed on basis of the Synchronous Data Flow and Pipelining. The Half Band IIR filters are used for high-performance applications. This design is processed to implement in FPGA which will result in higher speed and the cost will be variably decreased as well as the consumption of power. The entire process is implemented by using the Verilog language which reduces the complication and speeds up the whole process.

show abstract

High Speed Energy Efficient Multiplier Using 20nm FinFET Technology

Cited by 17 publications

References 0 publications

CSA Implementation Using Novel Methodology: RTL Development

CSA Implementation Using Novel Methodology: RTL Development

Digital Filter based Adder Module Realization High-Speed Switching Functions

FPGA based Digital Filter Design for faster operations

Contact Info

Product

Resources

About