High-Speed Fault Attack Resistant Implementation of PIPO Block Cipher on ARM Cortex-A

Abstract

In ICISC'20 conference, PIPO (Plug-In and Plug-Out) was proposed as an efficient block cipher for secure communication in IoT (Internet of Things) environment. Although PIPO equips easily high-order masking implementation because of small non-linear operations and short rounds, PIPO is still vulnerable to fault attack. For resisting the fault attack, block cipher implementation should be applied to the fault attack countermeasure. However, these techniques make the performance of computationallyintensive cryptographic algorithms slower in constrained devices. To improve this, we propose the first fast and secure software of PIPO block cipher co-designed with ARM/NEON processor for high-speed secure communication. For accelerating the performance, we present an optimal implementation of PIPO block cipher in ARM/NEON processor, respectively, and design the Interleaved way utilizing two cores. With the proposed optimal techniques, we provide the high-speed secure software. In addition, we present an interleaving random-shuffling technique, which optimizes random-shuffling by utilizing two cores. For ensuring the resistance of fault attacks, we validated the fault resistance with the computation and instruction fault model. We utilize the intra-instruction-redundancy and known ciphertext to detect them. Through the proposed contributions, the fast software for PIPO block cipher achieves the fastest performance than previous related studies. The secure software with the fault countermeasures is nearly 3 times faster than the reference implementation without any fault attack countermeasures. In addition, our secure software achieved performance improvement of 301% and 463% compared to the existing best work (HIGHT and revised CHAM). As a result, our fast and secure software for PIPO block cipher achieved the fastest performance by co-designing with two cores compared to previous work that is utilized only one core. Our software can be utilized for high-speed encrypted communication and CTR-DRBG in ARMv8-based IoT devices.

Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors

“…Accordingly, research on fault attack countermeasures of PIPO block cipher was conducted in the ARMv8 Cortex-A series environment. [4] presented a random-shuffling-based countermeasure for fault attack, and also proposed parallel optimization implementation using the NEON engine. Research on PIPO implementation is not actively conducted in environments that do not support SIMD instructions such as the NEON engine.…”

“…Accordingly, various studies are being actively conducted to evaluate the performance of PIPO from the perspective of implementation in various environments. Recently, research on the optimized implementation of PIPO equipped with countermeasures of sidechannel attack in the 8-bit AVR environment and parallel implementation of PIPO equipped with countermeasures of fault attack in the 64-bit ARM Cortex-A series were conducted [3], [4].…”