High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications

Khan, Safiullah; Javeed, Khalid; Shah, Yasir

doi:10.1016/j.micpro.2018.07.005

Cited by 30 publications

(17 citation statements)

References 15 publications

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“…In order to optimize PM, some works explored new opportunities in modular multipliers over binary fields, as modular multiplication is executed during the whole process of PM. Depending on the organization of computation, there are bitserial/ digit-serial, systolic multipliers, and bit-parallel multipliers [5], [6]. The complexity and latency (Clock Cycles, CCs) comparison are shown in Table 1.…”

Section: A Related Workmentioning

confidence: 99%

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

Wang

Zhang

et al. 2021

IEEE Access

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High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce's demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2 571 ) and GF(2 283 ) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2 571 ), which achieves one PM operation in 17.44 µs using 81549 LUTs (Look-Up-Table ) with the frequency of 197.2 MHz on Virtex-5, and 12.55 µs using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2 283 ) with the shortest computation time. It takes only 3.21 µs to finish one PM operation on Virtex-5 and 2.22 µs on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.INDEX TERMS Elliptic curve cryptography (ECC), dual-field point multiplication, montgomery ladder, field-programmable gate array (FPGA) implementation.

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Section: A Related Workmentioning

confidence: 99%

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

Wang

Zhang

et al. 2021

IEEE Access

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“…(1) KOA Fast Multiplication. e core idea of KOA [42] is "divide and conquer," i.e., a calculation approach in which a complex multiplication operation is decomposed into multiple simple multiplication operations by recursion. It is faster and more efficient than traditional calculation.…”

Section: Elliptic Curve Algorithmmentioning

confidence: 99%

Mimic Encryption Box for Network Multimedia Data Security

Zhou

et al. 2020

Security and Communication Networks

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With the rapid development of the Internet, the security of network multimedia data has attracted increasingly more attention. The moving target defense (MTD) and cyber mimic defense (CMD) approaches provide a new way to solve this problem. To enhance the security of network multimedia data, this paper proposes a mimic encryption box for network multimedia data security. The mimic encryption box can directly access the network where the multimedia device is located, automatically complete the negotiation, provide safe and convenient encryption services, and effectively prevent network attacks. According to the principles of dynamization, diversification, and randomization, the mimic encryption box uses a reconfigurable encryption algorithm to encrypt network data and uses IP address hopping, port number hopping, protocol camouflage, and network channel change to increase the attack threshold. Second, the mimic encryption box has a built-in pseudorandom number generator and key management system, which can generate an initial random key and update the key with the hash value of the data packet to achieve “one packet, one key.” Finally, through the cooperation of the ARM and the FPGA, an access control list can be used to filter illegal data and monitor the working status of the system in real time. If an abnormality is found, the feedback reconstruction mechanism is used to “clean” the FPGA to make it work normally again. The experimental results and analysis show that the mimic encryption box designed in this paper has high network encryption performance and can effectively prevent data leakage. At the same time, it provides a mimic security defense mechanism at multiple levels, which can effectively resist a variety of network attacks and has high security.

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“…One of the disadvantages of modular multiplication is that it required more time to complete the process. So Khan et al 21 proposed Karatsuba algorithm model in elliptic curve cryptosystem to improve its security measure. Also the proposed system processed the multiplication process for 192‐512 bits.…”

Section: Related Workmentioning

confidence: 99%

The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model

Srikanth

Kumar

Ravindra³

et al. 2020

Trans Emerging Tel Tech

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The multiplication strategy is a trending technology in chip programming model; also, it is used in different applications for different purpose. This research aims to develop the floating point double precision Furer Toom cook fast integer multiplication model in the Advanced Encryption Standard process round to enhance the security. In addition, the cryptography algorithms have been broken due to some harmful attack. So the main focus of this present research is to enhance the security measures in communication channel. Moreover, the proposed model is implemented in Xilinx and simulated in cadence 90 nm technology. By comparing the proposed work with recent existing models, the proposed research has reduced the power consumption as 5331.73 nW, thus 89% of power is reduced by the proposed Furer Toom cook multiplication model. The reduction of power enhanced the performance of multiplication algorithm so, while it is utilized in any application, it could not cause any loss of process. In addition, the developed strategy is process within 563 MHz frequency and utilized 11 250 cells. Thus, the proposed model provides better security for all wireless appliances.

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High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications

Cited by 30 publications

References 15 publications

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

Mimic Encryption Box for Network Multimedia Data Security

The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model

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