High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

Abstract

This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 lm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 lA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 lA, 0.99, -0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

A 1 V, 10 KS/S, 71.2 db SNDR current-mode CMOS sample-and-hold circuit for high-speed wireless communication applications

“…Current-mode circuit need lower input impedance which can be decreased by introducing the negative feedback [22], the special circuit is shown in Fig. 3, M 4 , M 5 and M 6 form the negative-loop, assuming the initial output impedance is Z 1 out , the improving impedance Z out is represented as follow formula, and the simulating result is shown in Fig.…”

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

“…Further, [31]- [34] employ various biasing techniques to reduce input impedance and hence achieve higher speeds of operation while maintaining lower power consumption. Specifically, simple biasing method is used in [31] and [33] whereas [32] uses negative feedback scheme at the transimpedance stage with an aim to achieve a very large loop-gain while maintaining the transformed voltage signal gain at the lowest swing in order to achieve speed…”

“…The quest to develop more efficient structures that meet the criteria of high speed and accuracy along with additional features such as low power dissipation is on-going. Authors have also proposed two such structures in [34]- [35]. In [34], a current comparator comprising a current difference stage, a gain stage with non linear feedback and an output stage has been proposed.…”

“…Authors have also proposed two such structures in [34]- [35]. In [34], a current comparator comprising a current difference stage, a gain stage with non linear feedback and an output stage has been proposed. It uses a current mirror structure as a current difference stage and a CMOS inverter is used as the output stage for rail to rail swing.…”