High-speed interconnect and packaging design of the IBM System z9 processor cage

Abstract

This paper describes the system packaging and technologies of the IBM System z9e enterprise-class server. The central electronic complex of the system consists of four nodes, each housing a multichip module (MCM) with 16 chips consuming up to 1,200 W. The z9e server doubles the multiprocessor performance of the System z990 by increasing the central processing unit (CPU) configuration and using an internally developed elastic interface to increase interconnect speed on all high-speed buses. In contrast to all previous zSeriest designs, which were running at half of the processor speed, the packaging interconnects on the multichip module run at the same speed as the processor (1.72 GHz). High frequencies and massively parallel connectivity lead to a raw packaging bandwidth of up to 1,764 GB/s between processors and cache within a single frame for a fully configured four-node z9 system.

Application of Vias as Functional Elements in Microwave Coupling Structures

“…Mostly good agreement can be observed. than 20 cavities are either very expensive or not realizable, high count multilayer structures (80 layers and more) might be found mostly in high integration ceramic packages [30], [31]. Fig.…”

Electronic packaging of the IBM System z196 enterprise-class server processor cage

“…There is no method available to measure these currents with the necessary precision and time resolution to transform into the frequency domain and then use this for the calculation of the power supply impedance in Eqn. (1).…”

“…With its general availability announced in September 2010, the IBM System z* 196 was introduced to the family of IBM System z high-end servers [1,2]. It replaces its predecessor, the IBM System z10* Enterprise Class (z10* EC), offers 50% higher symmetric multiprocessor (SMP) performance, and adds new features such as enhanced virtualization and new specialty engines, which were previously unavailable in System z high-end servers [3].…”

Challenges in Cooling Design of CPU Packages for High-Performance Servers

“…The thermal resistance of such a stacked design was verified to be lower than that of a direct chip to copper cap thermal paste design. In order to further reduce the thermal resistance between chips and the MCM cap, so-called small gap technology (SGT) is used in the IBM POWER5-based MCM packages and the z-Server MCM packages [10,11], where the MCM cap features the special cooling piston for each CPU chip, allowing a significant reduction of the gap between the chip and MCM cap. An alternative MCM cooling scheme was presented by Kobayashi et al [12] for the Hitachi M5800 high performance server, in which a dual-layer thermal interface design was applied between the chips and a micro-fin assembly, and then a common cap.…”