High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware

Efficient pipelined architecture for competitive learning

“…Moreover, the architecture uses the subspace search and bitplane reduction techniques to further reduce the area costs. It can then be observed Table 3 The area costs of the proposed architecture and the architecture in [24] for different numbers of neurons N. from Table 3 that the architecture in [24] has a lower consumption of LEs and embedded multipliers when the number of neurons N is large. Consequently, the SOPC based on the architecture in [24] also consumes lower hardware resources, as shown in Table 4.…”

“…The architecture presented in [24] is a hardware implementation of PDS in wavelet domain. Because of the employment of PDS, there is only one squared distance calculation unit in the circuit.…”

“…Although the architecture is able to perform online neuron updating in hardware, it can only process one training vector at a time. The existing digital architectures [24,28,29] for CL training therefore have only limited throughput.…”

“…For the comparison purpose, the area costs of the architecture presented in [24] are also included in Tables 3 and 4. The architecture presented in [24] is a hardware implementation of PDS in wavelet domain.…”

“…In [24], a digital hardware CL architecture based on hardware PDS in the wavelet domain [31] is proposed. Although the architecture is able to perform online neuron updating in hardware, it can only process one training vector at a time.…”