2017 IEEE 12th International Conference on ASIC (ASICON) 2017
DOI: 10.1109/asicon.2017.8252615
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High speed, low offset, low power differential comparator with constant common mode voltage

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Cited by 5 publications
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“…However, the bulk input design causes a leakage current to the predecessor stage. In addition, the design in [59] has approximately ten times longer delay while [60] requires a large area due to the use of resistors.…”
Section: Discussionmentioning
confidence: 99%
“…However, the bulk input design causes a leakage current to the predecessor stage. In addition, the design in [59] has approximately ten times longer delay while [60] requires a large area due to the use of resistors.…”
Section: Discussionmentioning
confidence: 99%