High-speed optoelectronic VLSI switching chip with &amp;lt;4000 optical I/O based on flip-chip bonding of MQW modulators and detectors to silicon CMOS

Lentine, Anthony L.; Goossen, K.W.; Walker, James Alfred; Chirovsky, L. M. F.; D'Asaro, L.A.; Hui, S.P.; Tseng, B.; Leibenguth, R.E.; Cunningham, J. E.; Jan, W.Y.; Kuo, J. M.; Dahringer, D.; Kossives, D.; Bacon, D. D.; Livescu, G.; Morrison, Rick L.; Novotny, R.A.; Buchholz, D. B.

doi:10.1109/2944.541876

Cited by 51 publications

(7 citation statements)

References 13 publications

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“…Secondly, we must trench isolate the top metal-dielectric stack-up above the ring and thereby disconnect a major lateral heat flow path in the photonic chip. Pit dimension(m) 7.5um 15um projection Figure 10. Thermal Tuning of stand alone ring modulators (unbonded) with BS pit of a specified opening.…”

Section: Hybrids With Integrated Thermal Tuningmentioning

confidence: 99%

mentioning

confidence: 99%

“…It has subsequently been refined for the integration of III-V modulators [6] and VCSELs [7] to CMOS circuits. Very high bump yield of better than 99.95% has been demonstrated with this approach [7], [8]. Previously [9,10], we reported on the hybrid integration by flip-chip attaching 130 nm SOI-CMOS photonic chips to 40 nm bulk CMOS ICs.…”

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confidence: 99%

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Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

Cunningham

Shubin

Thacker

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node of Freescale's SOI-CMOS technology while the CMOS driver circuits are fabricated in 40 nm TSMC ELK technology.The two types of chips are using 20 um diameter solder bumps. We further present progress on scaling these solder bumps to 10 micron diameter and below as well as developing a wafer scale microsolder process module.Finally, we report progress integrating hybrids that include SOI chips with a partially removed backside. Under full SOI handler removal this bonding geometry is akin to the extreme limit of wafer thinning used in today's vertical chip stacking (3D) approaches.

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Section: Hybrids With Integrated Thermal Tuningmentioning

confidence: 99%

mentioning

confidence: 99%

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Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

Cunningham

Shubin

Thacker

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…Solder bonding has been particularly successful. Large arrays (e.g., thousands) of quantum well modulator/photodiode devices have been successfully bonded to functioning silicon complementary metal-oxide-semiconductor (CMOS) VLSI circuits [44], [45]. Fig.…”

Section: Optical Interconnects To Silicon David a B Miller Fellowmentioning

confidence: 99%

Optical interconnects to silicon

Miller

2000

IEEE J. Select. Topics Quantum Electron.

311

130

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Abstract-This paper gives a brief historical summary of the development of the field of optical interconnects to silicon integrated circuits. It starts from roots in early optical switching phenomena, proceeds through novel semiconductor and quantum well optical and optoelectronic physics and devices, first proposals for optical interconnects, and optical computing and photonic switching demonstrators, to hybrid integrations of optoelectronic and silicon circuits that may solve basic scaling and other problems for interconnections in future information processing and switching machines.

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“…2 In real life applications, such as bar-code scanners, pattern recognition procedures, and counting currency, conventional mechanical systems have been replaced by more efficient optical methods. Currently, the paper money counter for old bills detects friction between the bill and the sensing pad, which creates dust, loud noises, and delays.…”

Section: Introductionmentioning

confidence: 99%

Optical sensing by using photonic quantum ring lasers and resonance-enhanced photodetectors

et al. 2002

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We describe an optical sensor using photonic quantum ring lasers and resonance-enhanced photodetectors for the purpose of counting object discrimination. Due to the angle-dependent peak wavelength shift characteristics of the photonic quantum ring laser, an emission at an angle of 0ϳ30 deg from a perpendicular direction was reflected and absorbed in the resonance-enhanced photodetector, with a peak responsivity of 0.107 A/W at 757 nm. The use of the photonic quantum ring laser at an optimized angle in this monolithically integrated system, based on a distributed Bragg partial reflector structure, can lead to a compact, low cost, dust-free optical sensor and counter.

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High-speed optoelectronic VLSI switching chip with <4000 optical I/O based on flip-chip bonding of MQW modulators and detectors to silicon CMOS

Cited by 51 publications

References 13 publications

Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

Scaling hybrid-integration of silicon photonics in Freescale 130nm to TSMC 40nm-CMOS VLSI drivers for low power communications

Optical interconnects to silicon

Optical sensing by using photonic quantum ring lasers and resonance-enhanced photodetectors

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