High-speed parallel-prefix module 2/sup n/-1 adders

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

“…Kalamboukas et al [5] have implemented Eqn. 2, to compute |A + B| 2 n -1 , via a totally parallel prefix (TPP) adder.…”

“…9a and inverting the polarity of the two least significant bits (i.e., regarding s 0 as S 0 , and vice versa). For TPP implementation, we can use the less complex TPP tree of [5] (Fig. 1b).…”

“…Weighted 2 n + 1 2 log n + 9 2 log n + 6 [1] Diminished-1 2 n + 1 2 log n + 7 2 log n + 5 [9] Signed-LSB 2 n + 1 2 log n + 7 2 log n + 5 New Weighted 2 n -1 2 log n + 5 2 log n + 3 [5] Signed-LSB 2 n -1 2 log n + 7 2 log n + 5 New …”

“…Moduli of the form 2 n ± 1, which greatly simplify certain RNS arithmetic operations have also been of longstanding interest. Over the years, many articles have been published on the design of modulo-(2 n ± 1) adders (e.g., [1], [2], [5]) and other arithmetic circuits, with new proposals still appearing on a regular basis [7]. This progression has gradually reduced the latency of such designs to the point of being quite competitive with ordinary (mod-2 n ) adders.…”

On building general modular adders from standard binary arithmetic components

“…Moduli of the form 2 δ are popular due to ease of designing fast adders, especially for δ 1 [14] and δ 3 [16], where addition circuits with only one n-bit adder in the critical path are possible. However, substantial effort may be needed for designing multiple arithmetic units for other δ (e.g., 5, 7, for n = 4) from scratch, including the laborintensive and error-prone optimization process for high speed and power economy in each case [2].…”