High‐speed parallel reconfigurable F_p multipliers for elliptic curve cryptography applications

Abstract

Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high-speed parallel re-configurable finite field multipliers: PIMD-2 and PIMD-3 over prime field (F p ) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high-speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD-2 and PIMD-3 designs are reduced simultaneously. The proposed F p multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex-5 and Virtex-6 field programmable gate array (FPGA) platforms for common ECC key sizes 160-521 bits. The implementation results reveal that the proposed designs are highly efficient, provided up to 3Â improvement in latency with lower area-delay product and higher throughput per FPGA slice as compared to the state-of-the-art. K E Y W O R D Selliptic curve cryptography, field programmable gate array, finite field multiplication, hardware accelerators, public key cryptography | INTRODUCTIONToday data security mechanism is essential in Internet of Things (IoTs) and must be developed considering computational power and resource availability of underlying systems. RSA 1 and elliptic curve cryptography (ECC) 2,3 are two popular public key (PK) schemes widely used for providing many interesting security protocols. [4][5][6] Different standardization bodies recommend ECC over RSA for deployment in the future. Different recommendations show that ECC key sizes are 10-30 times smaller than the traditional RSA scheme. 7 This key size gap is further expected to increase as the security challenges arise due to rapid advancement in the cryptanalysis techniques.RSA is an exponential scheme, and its implementation involves repeated finite field multiplication operation. On the other hand, ECC is structured on finite field addition, subtraction, multiplication, and inversion/division primitives. However, due to computational complexity of finite field inversion/division operations, different coordinate systems have been developed to avoid these operations at the cost of extra finite field multiplications. 5,8-10 Thus, a finite field

DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

“…A highperformance ECC processor architecture over curve448 is presented in [21], where a novel variant of the Karatsuba formula for asymmetric digit multiplier is incorporated for polynomial multiplications. The work described in [22] offers high-speed and reconfigurable polynomial multiplication architectures for specific prime fields. A high-speed point multiplier for Goldlilocks-curve448 is presented in [23].…”

EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

“…Several pertinent modifications and associated hardware architectures [19], [20], [24], [30], [33], [35] have been proposed for the R2IM algorithm. References [19], [30], and [33] are executing single iteration in one clock cycle while [19], [24], and [35] are based on radix-4, where two consecutive bits of a multiplier are executed in a single clock cycle. Moreover, [20] and [24] reduced the data dependency among critical operations and executed them in parallel.…”

“…References [19], [30], and [33] are executing single iteration in one clock cycle while [19], [24], and [35] are based on radix-4, where two consecutive bits of a multiplier are executed in a single clock cycle. Moreover, [20] and [24] reduced the data dependency among critical operations and executed them in parallel. However, these designs employed multiple processing units for the generation, reduction, and addition of possible partial products.…”

“…Several useful modifications and related architectures have been proposed for all these three approaches [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30]. Designs reported in [14], [15], [16], [21], [22], [23], [25], [26], and [27] are based on MM, [19], [20], [24], [28], [29], [30] are based on IM and [17], [18] are using NIST recommended SP primes. Most of these designs are then further utilized in the development of several ECPM architectures [17], [19], [20], [21], [30], [31], [32], [33], [34], [35], [36], [37], [38].…”

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

“…In previous works, modular multipliers are based on MM 27,[43][44][45][46][47] while others are developed using the IM method. 25,29,31,33,[48][49][50][51][52] In these designs, several modifications have been introduced to reduce computational delay and hardware area occupation such as carry-save addition, residue number system (RNS), redundant sign digit (RSD) system, and even some designs utilizing built-in components of the modern FPGAs.…”