High-speed photodiodes in 40nm standard CMOS technology

Atef, Mohamed; Polzer, A.; Zimmermann, Horst

doi:10.1016/j.sna.2013.01.037

Cited by 6 publications

(1 citation statement)

References 16 publications

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“…The simplest way to build CMOS photodiodes is to use the classical PN junctions available in CMOS processes: source or drain/substrate, and well/substrate diodes. Figure 9 shows the structure of the proposed PDs fabricated with a standard 40nm CMOS process [14]. In Fig.…”

Section: 1classical Pn Junctionsmentioning

confidence: 99%

Integrated Photodiodes in Nanometer CMOS Technologies

Atef¹

2014

ELELIJ

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The main speed limitations of standard nanometer CMOS photodiodes are coming from the substrate slow carriers diffusion. Also the capacitance of the photodiode is increasing with technology scaling as the doping is increasing. The PD capacitance must be as low as possible to reduce the high frequency loss of the photocurrent to reach highest possible sensitivity. These demands are partially conflicting; so a trade-off is necessary, especially due to the wavelength dependence of the penetration depth. Many photodiode structures are recently introduced to increase the photodiode intrinsic speed in nanometer CMOS technology. In this paper a theoretical and comparative study for different recently published photodiodes structures fabricated in nanometre CMOS technology will be presented. This paper gives the researchers a detailed comparison and analysis to select the right photodiode to achieve the best performance in challenging nanometre CMOS technology.

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Section: 1classical Pn Junctionsmentioning

confidence: 99%