High-Speed Polynomial Basis Multipliers Over GF(2 m ) for Special Pentanomials

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

2018

Self Cite

Hardware implementations of arithmetic operations over binary finite fields GF (2 m) are widely used in several important applications, such as cryptography, digital signal processing and error-control codes. In this paper, efficient reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f (y) = y m + y n+2 + y n+1 + y n + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for GF (2 m) multiplication based on type II pentanomials is given and several post-place and route implementation results in Xilinx Artix-7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area×time parameter when compared with similar multipliers found in the literature.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconfigurable implementation of GF(2^m) bit-parallel multipliers

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

2018

Self Cite

“…The addition of these functions is used for the computation of the product of two GF (2 m ) elements. In [3], the above method was applied to type II irreducible pentanomials and the functions S i and T i were split in the form (2) and k = log 2 m . The terms S j i and T j i represent the sum of 2 j products a k b l and therefore can be implemented as a j-level complete binary tree of XOR gates.…”

mentioning

confidence: 99%

“…In this work, efficient Xilinx FPGA implementations of GF (2 m ) bit-parallel polynomial basis multipliers for irreducible trinomials are presented. Based on [2], a new general algorithm for multiplication over irreducible trinomials f (y) = y m + y n + 1, with 1 ≤ n ≤ (m + 1)/2, is proposed and the splitting method given in [3] is applied to these irreducible polynomials. Furthermore, in order to optimize the synthesis of the multipliers, a new approach for the computation of the product is used where the splitting of S i and T i terms is performed, but the restriction given by the addition in pairs of binary trees with the same depth has been removed.…”

mentioning

confidence: 99%

Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials

2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

2018

Self Cite

Binary extension (or Galois) fields GF (2 m ) have been widely studied due to their use in several important applications, such as cryptography, error control codes and digital signal processing. These applications require efficient hardware implementations of GF (2 m ) arithmetic operations, particularly multiplication, which is considered the most important and complex one. The complexity of GF (2 m ) multiplication depends on the representation basis and on the defining irreducible polynomial f (y) selected for the finite field. For efficient hardware implementations, polynomial basis and irreducible trinomials or pentanomials are normally used. Any element A ∈ GF (2 m ) can be represented in the polynomial basis {1, x, . . . ,, where x is a root of the irreducible polynomial f (y) = m i=0 f i y i . Polynomial basis multiplication C = A · B requires a polynomial multiplication followed by a reduction modulo an irreducible polynomial. Mastrovito [1] proposed an efficient bit-parallel polynomial basis multiplier in which a product matrix was introduced to combine the above two steps together. A new polynomial basis multiplication method applied to irreducible trinomials was proposed in [2], where the functions S i and T i given by the addition of terms x k = (a k b k ) and z j i = (a i b j + a j b i ), with a i , b i ∈ GF (2), were obtained from the decomposition of a product matrix. The addition of these functions is used for the computation of the product of two GF (2 m ) elements. In [3], the above method was applied to type II irreducible pentanomials and the functions S i and T i were split in the form(2) and k = log 2 m . The terms S j i and T j i represent the sum of 2 j products a k b l and therefore can be implemented as a j-level complete binary tree of XOR gates. The addition in pairs of binary trees with the same depth leads to a reduction of the multiplication delay. However, splitting method imposes hard restrictions (given by the use of parenthesis in the expressions of the coordinates) for the addition of S j i and T j i terms in order to reduce the number of XOR levels. These restrictions could not be efficient for a synthesis tool in order to map that expressions into FPGA's logic blocks. If parenthesized restrictions are removed, more freedom could be given for the synthesizer to find an optimized implementation of the multiplier.In this work, efficient Xilinx FPGA implementations of GF (2 m ) bit-parallel polynomial basis multipliers for irreducible trinomials are presented. Based on [2], a new general algorithm for multiplication over irreducible trinomials f (y) = y m + y n + 1, with 1 ≤ n ≤ (m + 1)/2, is proposed and the splitting method given in [3] is applied to these irreducible polynomials. Furthermore, in order to optimize the synthesis of the multipliers, a new approach for the computation of the product is used where the splitting of S i and T i terms is performed, but the restriction given by the addition in pairs of binary trees with the same depth has been removed. In this way, X...

“…In [6], the functions S i and T i were given as a sum of S j i and T j i terms in such a way that S i = s i r S p i + . .…”

mentioning

confidence: 99%

Low‐delay AES polynomial basis multiplier

2016

Electron. lett.

In this Letter, an efficient implementation of the bit-parallel polynomial basis (PB) multiplier over the binary field GF(2 8 ) generated by the type I irreducible pentanomial f (y) = y 8 + y 4 + y 3 + y + 1 is presented. This pentanomial is especially important because it is used in the advanced encryption standard (AES). Therefore, any optimisation of the multiplier complexity over this finite field is very relevant because efficient AES implementation can be obtained. The bit-parallel multiplier here presented has the lowest delay known to date for similar multipliers based on this irreducible pentanomial.Introduction: High-speed hardware implementations of arithmetic operations in the Galois field GF(2 m ) are greatly desirable due to their use in several important applications, such as cryptography, coding theory and digital signal processing. Among arithmetic operations, the multiplication is the most important one because division, inversion and exponentiation can be performed by repeated multiplications. Many architectures have been proposed to perform GF(2 m ) multiplication in which different representation basis of field elements have been used. Among them, polynomial basis (PB) is the most widely used. The complexity of the multiplier greatly depends on the basis used and on the generating irreducible polynomial f(y) selected for the finite field. For hardware implementation, trinomials and pentanomials are usually used. For irreducible trinomials, multipliers with low area and time complexities can be implemented [1,2]. Unfortunately, an irreducible trinomial does not exist for every value of m. In such cases, an irreducible pentanomial can be found.PB multiplication requires a polynomial multiplication followed by a modular reduction. Efficient bit-parallel multipliers can be implemented introducing a product matrix that combine the above two steps together [1][2][3][4]. In [5], a new PB multiplication method based on the decomposition of a product matrix was used. This method introduced the functions S i and T i given by the sum of product terms. The coefficients of the product of two field elements can be computed as the sum of that functions. In [6], the sum of products given in the S i and T i functions were separated into sums of 2 j product terms that can be implemented as binary trees of XOR gates with depth j. The sum in pairs of binary trees with the same depth, starting with the lower levels, leads to a reduction of the delay. The multiplication approach in [6] was applied to type II irreducible pentanomials f (y) = y m + y n+2 + y n+1 + y n + 1.In this Letter, a new high-speed bit-parallel GF(2 8 ) multiplier is presented, where the splitting of the S i and T i functions has been applied to the type I irreducible pentanomial f (y) = y 8 + y 4 + y 3 + y + 1. This pentanomial is especially important because it is used in the advanced encryption standard (AES). Furthermore, the specific field GF(2 8 ) has been standardised for space communication by ESA and NASA and used in CD players. The n...