High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

Abstract

A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

“…Among these amplifiers there are unity-gain zero-offset buffers characterized by zero offset between input and output voltages [1][2][3][4][5][6][7][8]. Unity-gain zero-offset buffers have found application in the testing of analogue chips [8], in analogue filtering [9][10][11], oscillators [12], voltage regulators [13,14], and in LCD panels [15,16]. Most of these buffer solutions use the classic approach based on a high-gain differential amplifier and a negative feedback to obtain unity gain and zero offset.…”

High-Speed Column Driver IC Having Buffer Amplifier with Embedded Isolation Switch and Compact Adaptive Biasing for Flat-Panel Displays

“…Moreover, the dot inversion method typically requires explicit components such as polarity multiplexer switches to alternate the LC polarity, which can degrade the panel driving speed. Actually, in the FPD column driver, the time for panel driving is critical since it must not exceed the horizontal scanning pattern time [19][20][21][22][23][24][25][26].…”

“…To satisfy these requirements, class AB or B amplifiers [18][19][20][21][22][23][24][25][26] have been widely used as output buffer amplifiers in FPDs. In this case, there can be numerous issues concerning explicit switch on-resistance, high-slew-rate amplifier design, adaptive biasing circuit design, and the resulting overheads in terms of area and power consumption.…”

“…Thus, the power consumption increases as the bias current increases to provide a higher slew-rate. The class AB amplifiers with various adaptive biasing schemes have been proposed to improve the slew-rate without having a large input bias current [21,22,26]. In [21,22], the settling time is reduced but the circuit for implementing the adaptive biasing requires so many transistors, resulting in increased power consumption and chip area.…”

“…In [21,22], the settling time is reduced but the circuit for implementing the adaptive biasing requires so many transistors, resulting in increased power consumption and chip area. In [26], the number of transistors for implementing the adaptive biasing has been reduced from 26 to 10 as compared to [22]. However, the area overhead is not small enough since there are still many current mirror transistors used.…”