High speed switch scheduling for local area networks

Abstract

Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in xed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram tra c. In addition, it supports real-time tra c by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of con ict-free cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch b y building a xed schedule for transporting cells from reserved ows across the switch; parallel iterative matching can ll unused slots with datagram tra c. Finally, w e note that parallel iterative matching may not allocate bandwidth fairly among ows of datagram tra c. We describe a technique called statistical matching, which can be used to ensure fairness at the switch and to support applications with rapidly changing needs for guaranteed bandwidth.

Parallel desynchronized block matching: A feasible scheduling algorithm for the input-buffered wavelength-routed switch

“…The design of the Parallel Desynchronized Block Matching (PDBM) scheduling algorithm, presented in this section, is a sample of this. Specifically, PDBM adapts implementation concepts present in the parallel-iterative VOQ schedulers [18], [20] and especially [21]. Figure 3 shows the electronic implementation proposed for the PDBM scheduler.…”

Diffusion Approximation for an Input-queued Switch Operating under a Maximum Weight Matching Policy

“…The use of VOQs avoids the so-called head-of-line blocking phenomenon (cf. [1] and [11]). Thus, there are N 2 separate VOQs, one for each input-output pair.…”

Throughput analysis of shared-memory crosspoint buffered packet switches

“…S q matches non-empty inputs to SMBs that have room for storing at least one cell. The matching in S q follows a three-phase process, as that used by some IQ switches [27], [29]. In this section, the matching scheme in S q uses random selection [27].…”

“…The matching in S q follows a three-phase process, as that used by some IQ switches [27], [29]. In this section, the matching scheme in S q uses random selection [27]. A credit-based flow control is used to monitor the available space in SMBs and to avoid buffer underflow.…”

“…In these switches, one of them uses dynamic partitioning of buffer space and speedup of m, and it is called the SMCBxm switch, and the other arbitrates inputs to access the shared crosspoint buffers to avoid memory speedup, and it is called the mSMCB switch. Random selection has been used to analyze the throughput of packet switches [27], [28] and here, we adopt it for a similar reason. The analysis proves that the achievable throughput of the two shared memory CICB switches is 100% under i.i.d.…”