High speed vedic multiplier for image processing using FPGA

High Speed Vedic Multiplier Based Review With Its Proposed Implementation for Parallel Fir Filter

“…A technique of Vedic mathematics has been used to reduce power in image processing application [8]. The Vedic algorithm is implemented in image filtering to enhance the image quality.…”

“…Multipliers are the commonly used architectures inside the processor. Multiplier is also applicable in digital filtering [2] and various image processing application [8]. Since multiplication dominates the execution time of most DSP algorithms, use of high speed multiplier is very desirable.…”

Extended overlay architectures for heterogeneous FPGA cluster management

“…Nowadays, hardware architectures, especially the ones dedicated for signal and image processing, must offer high performance computation, design flexibility, and upgrade capabilities. Reconfigurable chips, such as Field Programmable Gate Arrays (FPGAs), have been addressed as a reasonable solution in this area, combining flexibility, re-programmability, power efficiency, and low development cost [1,2] .…”