The data communications industry has developed optical link standards options for 10 Gbit/s using VCSEL based transmitters, and the next step is cost effective 40 Gbit/s links. Parallel link options [l] have been proposed, but the 10 Gbit/s link experience has taught that if serial links can be made they will be most cost effective, and being closer to serial is better than being slower and wider. This raises the question of acheiving 4OGb/s using two VCSELs at 2OGb/s each as a possible cost effective solution. Numerous groups have demonstrated large signal modulation of VCSELs up to 12.5Gb/s (i.e.[2], [3]) and up to 15.6Gbh [4]. This paper reports on experiments driving VCSEL based optical links to %OGb/s which is the fastest known VCSEL link driven by 3 volt IC's and operating over premises length multimode fiber.The VCSEL used in this experiment is an oxide confined device with an 8um oxide aperture. The device is fabricated on a semi-insulating substrate with two planar topside contacts. At room temperature the threshold current is 0.3mA and the slope efficiency is 0.29mW/mA. Thermal rollover begins at 6.2mA due to the high thermal impedance of 1700 WW. The maximum cw optical power is 1.3 mW. The series resistance in the range of operation is 145 Ohms. The device is primarily single mode at 843nm although three side modes exists at -10, -1 1 and -1 8dB down respectively under cw and ac conditions. Figure 1 is a plot of the small signal response as a h ction of bias. At 6.2mA the -3dB frequency is 15.4GHz. The modulation efficiency is 13.7 GHd root(mW) up to 1.2mA( 10GHz) and then begins to saturate.The device is directly connected to a driver IC through two short (500pm) wirebonds. The VCSEL driver is implemented in a 0.5um SOGHz fT SiGe bipolar technology. The driver utilizes fully differential circuits including an onchip AC coupling network to the VCSEL load. DC bias control is also provided on the driver thereby eliminating the need for any external passives between the driver and VCSEL. This permits the use of an unterminated network between the two parts since the lack of any off-chip passives allows for very small physical separations. The total power dissipation running at 20Gb/s is typically 180mW at 3 . 3~. To optimize the circuit design, a rate equation based model of the VCSEL including an impedance model similar to [5] implemented in spice was used. Figure 2 shows the back to back optical eye diagram from the VCSEL (top trace) and the electrical signal that is fed to the driver IC (bottom trace). The deterministic jitter (DJ) of the source is 9.5~~3, the rise and fall times (20-80) are 20 ps (undeconvolved from 13ps oscilloscope 10-90 risetime) and the intersymbol interference (ISI) is 0.93dB. At 2m, the DJ from the VCSEL is 15.5~s and the IS1 is 2.64dB. Some eye closure (ISI) is expected from the VCSEL as the 15GHz bandwidth of the device attenuates much of the high frequency part of the dnving signal. Figure 3 shows the averaged eye diagram at 200m. The additional accumulated IS1 over 200m is ...