“…Higher timing resolution also allows reduced dead-time and switching transition time of the switching node, which can reduce P DT and P ST , respectively. On the other hand, the voltage ratings of the thin oxide FET in the advanced technology node is typically around 1V, thus, V IN beyond this voltage requires FETstack power stage [13], [14], [25], [30], [31], [34], [35], [37], [38], [41]- [46], [48]- [50], [67] as shown in Fig. 5.…”