Solar Power 2012
DOI: 10.5772/30682
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High Temperature Annealing of Dislocations in Multicrystalline Silicon for Solar Cells

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Cited by 7 publications
(13 citation statements)
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“…Then, all samples were annealed at 820 • C for 2 h in air using the same temperature profile of the first experiment. Table I summarizes sample preparation and experimental procedure for all samples. For all samples in both sample sets, 1 mm of the surface was removed by mechanical polishing after annealing to fully remove the gettering layer and to reveal bulk regions, where the effect of image forces on dislocation motion is negligible [19]. To reveal crystal defects, all samples were etched in a volumetric ratio mixture of 9:0:1 (nitric, acetic and hydrofluoric acid, respectively), then agitated in a Sopori etch (2:15:36) [29] for 30 s, and finally quenched in 9:0:1 mixture for 1-2 s. This process leads to the formation of small dislocation etch pits, where dislocations intersect the surface of the silicon wafer.…”
Section: Methodsmentioning
confidence: 99%
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“…Then, all samples were annealed at 820 • C for 2 h in air using the same temperature profile of the first experiment. Table I summarizes sample preparation and experimental procedure for all samples. For all samples in both sample sets, 1 mm of the surface was removed by mechanical polishing after annealing to fully remove the gettering layer and to reveal bulk regions, where the effect of image forces on dislocation motion is negligible [19]. To reveal crystal defects, all samples were etched in a volumetric ratio mixture of 9:0:1 (nitric, acetic and hydrofluoric acid, respectively), then agitated in a Sopori etch (2:15:36) [29] for 30 s, and finally quenched in 9:0:1 mixture for 1-2 s. This process leads to the formation of small dislocation etch pits, where dislocations intersect the surface of the silicon wafer.…”
Section: Methodsmentioning
confidence: 99%
“…This calculation is well matched with the measurements in the present study for samples from set A annealed without a P layer, that is, 1.03 ± 0.07, 1.08 ± 0.09, and 0.97 ± 0.08 after annealing at 820, 920, and 1020 • C for 2 h, respectively. Annealing at such low temperatures has been reported to have negligible effect on dislocation annihilation [16]- [19]. Moreover, at temperatures below 1000 • C, it has been known that dislocations cannot move freely because limited vacancy migration inhibits dislocation climb [37], [38], limiting dislocation pairwise annihilation.…”
Section: A Effect Of Dislocation-impurity Interactions On Dislocatiomentioning
confidence: 99%
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“…An image force on the sample surface may help to annihilate more dislocations. Stokkan et al [122] found a significant reduction in dislocation density near the sample surface (to a depth of $ 50 mm from the surface), presumably due to the presence of an image force.…”
Section: Effect Of External Stressmentioning
confidence: 97%
“…A number of metal impurities may impede dislocation annihilation processes in the top of the ingot. Stokkan et al [122] reported that annealing of mc-Si at 1350°C for 4 h [120] UMG-Si ingot Annealing temperature: 1160, 1260, 1360°C…”
Section: Physics Of Dislocation Activitiesmentioning
confidence: 99%