High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors

Emam, Mostafa; Tinoco, J. C.; Vanhoenacker‐Janvier, Danielle; Raskin, Jean‐Pierre

doi:10.1016/j.sse.2008.06.058

Cited by 30 publications

(14 citation statements)

References 23 publications

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“…The two main assumptions made by Bracale [20] are: (i) the constant carrier mobility behavior respect to the transversal electric field and (ii) the perfect symmetry of the MOSFET (C gs 5 C gd ) at V ds 5 0 V. First, for sub-100 nm MOSFET characterized by an ultrathin gate oxide the constant carrier mobility as a function of V gs is not valid anymore. Secondly, in practice the perfect symmetry of the transistor at V ds 5 0 V it is not always assured because of contact and interconnection asymmetry between the source and drain areas [25,26].…”

Section: New Extraction Methodsmentioning

confidence: 99%

New RF extrinsic resistances extraction procedure for deep‐submicron MOS transistors

Tinoco

Raskin

2009

Int J Numerical Modelling

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SUMMARYThe modeling of MOS transistors used for RF applications needs the definition of a lumped equivalent circuit where the intrinsic device and series extrinsic resistances are properly evaluated. The model accuracy depends on the extraction precision of each intrinsic lumped element. In order to determine the intrinsic device behavior, it is necessary to first remove the series extrinsic resistances. For this reason their extraction becomes critical for the modeling of MOS transistors in RF circuit design. Several extraction methods have been proposed; nevertheless, the measurement noise strongly affects the obtained results. The method proposed by Bracale and co-workers is the most robust extraction procedure against measurement noise, but fails to predict correctly the series extrinsic resistances for deep-submicron devices. For those reasons, we deeply analyze the method proposed by Bracale in order to understand and then overcome its limitations. Based on those analyses, a robust extraction method for deep-submicron devices is proposed.

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Section: New Extraction Methodsmentioning

confidence: 99%

New RF extrinsic resistances extraction procedure for deep‐submicron MOS transistors

Tinoco

Raskin

2009

Int J Numerical Modelling

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“…The reported behavior can be ascribed to the counterbalancing of the degradation of the electron transport properties at higher temperature and the shift in the threshold voltage. As can be observed in Figures and , the so called zero temperature coefficient (ZTC) point for g m can be defined for both devices as the point at which g m stays constant as temperature changes .…”

Section: The Active Role Of the Transconductancementioning

confidence: 99%

The large world of FET small-signal equivalent circuits (invited paper)

Crupi

Caddemi

Schreurs

et al. 2016

Int J RF and Microwave Comp Aid Eng

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The small-signal equivalent circuit modeling of microwave field-effect transistors (FETs) is an evergreen and ever flourishing research field that has to be up-to-date with technological developments. Hence, modeling techniques must be continuously adapted and extended to suit best evolving technologies. The extraction of a FET high-frequency small-signal equivalent circuit is a very active and broad research area of significant interest, owing to its use as a prerequisite for noise and large-signal modeling. The aim of this invited article is to provide in-depth knowledge, critical understanding, and new insights into how to extract a FET small-signal equivalent circuit from both theoretical and practical perspectives. To illustrate potential solutions to the key challenges faced by researchers, experimental results for different semiconductor technologies are reported and discussed. The study is focused on the hot research topic of the cold approach that has been, and still is, the most widely used technique for extracting FET small-signal models and on the active role of the transconductance for successful modeling. V C 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:749-762, 2016.

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“…In a FinFET device, the decrease of threshold voltage with temperature tends to increase drain current in weak inversion while the mobility reduction causes a decrease in strong inversion [22,23]. A gate bias point exists when these opposing effects compensate each other, thus exhibiting the socalled ZTC (zero temperature coefficient) point [24,25]. The ZTC In particular, the transconductance was first increased and then decreased with increasing gate voltage at V DS = 0.1 V (Fig.…”

Section: Device Simulation Using Silvaco-atlasmentioning

confidence: 99%

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator ATLAS™ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/ off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

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High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors

Cited by 30 publications

References 23 publications

New RF extrinsic resistances extraction procedure for deep‐submicron MOS transistors

New RF extrinsic resistances extraction procedure for deep‐submicron MOS transistors

The large world of FET small-signal equivalent circuits (invited paper)

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

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