High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

Abstract

High-temperature electrical performances of enhancement-mode (E-mode) high electron mobility transistor with ptype Gallium Nitride (GaN) gate cap are evaluated here. The physics-based mechanisms behind the behaviours are also analysed by the simulations and analytical models. For static electrical performances, the changes of GaN bandgap and the interface states or traps are considered to be influential factors for the little variations of threshold voltage (V T). Meanwhile, the on-state resistance increases and trans-conductance decreases at high temperatures due to the reduction in electron mobility (µ eff). As for blocking characteristic, high temperature-induced increase of leakage current may result from multi-reasons, such as the increase of intrinsic carrier concentration and lowering of trap barrier. In addition, a segmental method is presented to understand the gate leakage current at high temperatures. For capacitance characteristics, the increase of channel resistance makes the measured gate capacitance lower than the intrinsic value. For dynamic electrical performances, the high temperature-induced decrease of µ eff leads to the increase of plateau voltage, bringing the decreases of total switching time and total switching energy loss, which are quite different from those of the devices with traditional metal-oxide-semiconductor structures.

Status and prospects of wide bandgap semiconductor devices

“…The conductivity of GaN increases with temperature due to the increased ionization of impurities and defects, which produces free carriers. Researchers [38] also found that the high-temperature p-GaN HEMT devices threshold voltage fluctuations are minor and mainly impacted by GaN's bandgap and interface states or obstacles. The decline in transconductance and rise in on-resistance primarily originate from the reduction in carrier mobility.…”

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

“…The physical mechanism behind the degradation effects for pulsed and prolonged V GS bias stress on the p-GaN gate HEMT is explained in the Figure 9a,b. In view of the Schottky gate contact of the studied device, where the metal/p-GaN hetero-structure acts as Schottky junction diode and the p-GaN/AlGaN/GaN structure acts as p-i-n junction diode, and respective junction capacitances [38,39]. Under negative gate bias, the J Schottky is forward biased, with small voltage drop on it.…”

Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

“…Due to the Schottky gate contact of the p-GaN gate HEMTs, the metal/p-GaN structure performs as a Schottky diode (D J1 in figure 8), the p-GaN/AlGaN/GaN structure performs as a p-i-n diode (D J2 in figure 8), and C J1 and C J2 are the junction capacitances of D J1 and D J2 , respectively [16]. At the reverse gate bias, the D J1 is forward-biased with a decreased depletion width in the p-GaN layer.…”

“…At a high temperature, ionized holes in the p-GaN cap will also increase [16]. At the same negative V gs bias, ionized holes in the p-GaN cap can provide a more positive charge to balance the voltage drift induced by the negative gate voltage.…”