High‐throughput and compact reconfigurable architectures for recursive filters

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels.

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High‐throughput and compact reconfigurable architectures for recursive filters

Cited by 3 publications

References 10 publications

Efficient Filter Implementation Using Cutset Retiming and Pipelining Approaches

Efficient Filter Implementation Using Cutset Retiming and Pipelining Approaches

A Novel Approach for Excitation Codebook and Perceptual Weighting Filter Design

Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

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